公开(公告)号：US5436483A

公开(公告)日：1995-07-25

申请号：US142965

申请日：1993-10-29

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US4295265A

公开(公告)日：1981-10-20

申请号：US58501

申请日：1979-07-18

申请人： Masatada Horiuchi ,  Hisao Katto

发明人： Masatada Horiuchi ,  Hisao Katto

IPC分类号： H01L27/112 ,  H01L21/26 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28

CPC分类号： H01L29/1041 ,  H01L21/26 ,  H01L29/7883

摘要： In a nonvolatile semiconductor memory which comprises a source region and a drain region formed on one surface of a semiconductor substrate having one conductivity type, a first insulating film formed on a channel region which is located between the source region and the drain region, a floating gate formed on at least a portion of the first insulating film and which is electrically floated, a control gate formed on the floating gate via a second insulating film, and high impurity concentration regions formed in or near a portion of the channel region and having the same conductivity type as that of the substrate, the floating gate is formed prior to the high impurity concentration regions, and the high impurity concentration regions are formed just outside the channel region by self-alignment with said floating gate using said floating gate as part of a mask.

摘要翻译： 在包括形成在具有一种导电类型的半导体衬底的一个表面上的源区和漏区的非易失性半导体存储器中，形成在位于源区和漏区之间的沟道区上的第一绝缘膜，浮置 形成在第一绝缘膜的至少一部分上并被浮置的栅极，经由第二绝缘膜形成在浮置栅极上的控制栅极和形成在沟道区域的一部分中或附近的高杂质浓度区域，并且具有 与基板相同的导电类型，在高杂质浓度区之前形成浮栅，并且通过使用所述浮栅与所述浮置栅极进行自对准而将高杂质浓度区形成在沟道区的正上方，作为 一个面具

公开(公告)号：US5580810A

公开(公告)日：1996-12-03

申请号：US416099

申请日：1995-04-04

申请人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

发明人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/8247

CPC分类号： H01L23/522 ,  G11C5/025 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/922 ,  Y10S257/925 ,  Y10S438/926

摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.

摘要翻译： 一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。 布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。 布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

公开(公告)号：US4652897A

公开(公告)日：1987-03-24

申请号：US754961

申请日：1985-07-15

申请人： Kousuke Okuyama ,  Kazuhiro Komori ,  Hisao Katto

发明人： Kousuke Okuyama ,  Kazuhiro Komori ,  Hisao Katto

IPC分类号： H01L21/8247 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7835 ,  H01L29/7885

摘要： A semiconductor memory device wherein a portion of source region of a field-effect transistor that serves as a memory cell has a low impurity concentration, so that hot carriers generated on the source side are injected into the floating gate. Hot carriers are generated by utilizing a large electric field intensity established by the drop of voltage in the region of low impurity concentration. The voltage difference is so great between the source region and the control gate that hot carriers generated on the source side are efficiently injected into the floating gate.

摘要翻译： 一种半导体存储器件，其中用作存储单元的场效应晶体管的源极区域的一部分具有低的杂质浓度，使得在源极上产生的热载流子注入浮置栅极。 通过利用由低杂质浓度区域内的电压降而建立的大电场强度来生成热载流子。 在源极区域和控制栅极之间的电压差很大，源极上产生的热载流子被有效地注入到浮动栅极中。

公开(公告)号：US5436484A

公开(公告)日：1995-07-25

申请号：US143151

申请日：1993-10-29

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US5416347A

公开(公告)日：1995-05-16

申请号：US959534

申请日：1992-10-13

申请人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

发明人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/772

CPC分类号： H01L23/522 ,  G11C5/025 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/922 ,  Y10S257/925 ,  Y10S438/926

摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.

摘要翻译： 一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。 布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。 布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

公开(公告)号：US5276346A

公开(公告)日：1994-01-04

申请号：US815863

申请日：1992-01-02

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatoc protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 本发明公开了一种半导体器件，其具有由静电场保护电路保护的内部电路，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一个实施例，提供一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US4830977A

公开(公告)日：1989-05-16

申请号：US148956

申请日：1988-01-27

申请人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

发明人： Hisao Katto ,  June Sugiura ,  Nozomi Horino ,  Akira Endo ,  Yoshiharu Takeuchi ,  Yuji Arakawa

IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L23/522 ,  G11C5/025 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/922 ,  Y10S257/925 ,  Y10S438/926

摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.

摘要翻译： 一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。 布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。 布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

公开(公告)号：US5116775A

公开(公告)日：1992-05-26

申请号：US396686

申请日：1989-08-22

申请人： Hisao Katto ,  Jun Sugiura

发明人： Hisao Katto ,  Jun Sugiura

IPC分类号： H01L27/08 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76218 ,  H01L21/74 ,  H01L27/10805 ,  H01L27/105 ,  Y10S438/953

摘要： A heavily-doped semiconductor region and a channel stopper region, which are disposed under a memory cell in a memory cell region, are simultaneously formed after formation of a field insulator film, thereby preventing the channel stopper region from oozing out into the channel region, and thus obtaining a semiconductor memory device which is resistant to .alpha.-rays and therefore free from soft errors caused by .alpha.-rays. Also disclosed is a method of producing said semiconductor memory device.

摘要翻译： 在形成场绝缘膜之后，同时形成设置在存储单元区域中的存储单元下方的重掺杂半导体区域和沟道截止区域，从而防止沟道阻挡区域渗入沟道区域， 从而获得耐受α射线的半导体存储器件，因此没有由α射线引起的软错误。 还公开了一种制造所述半导体存储器件的方法。

公开(公告)号：US4904615A

公开(公告)日：1990-02-27

申请号：US301978

申请日：1989-01-26

申请人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

发明人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

IPC分类号： H01L27/112 ,  H01L21/8246

CPC分类号： H01L27/1126

摘要： Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.