公开(公告)号：US20120155178A1

公开(公告)日：2012-06-21

申请号：US13235435

申请日：2011-09-18

申请人： Hitoshi OHTA ,  Mitsuhiro Abe ,  Eiji Kozuka ,  Takatomi Izumi

发明人： Hitoshi OHTA ,  Mitsuhiro Abe ,  Eiji Kozuka ,  Takatomi Izumi

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C7/10

CPC分类号： G11C11/005 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C2207/2245

摘要： According to one embodiment, a semiconductor memory device includes a memory, and a data transfer section configured to perform data transfer from and to the memory, and having a first mode to transfer data with a first bit width and a second mode to transfer data with a second bit width. The data transfer section includes a first latch circuit configured to hold first data read from the memory, a second latch circuit configured to hold second data having the first bit width of the first data in the first mode, and to hold third data having the second bit width of the first data in the second mode, and data bus connecting the first latch circuit to the second latch circuit and shared by the first and second modes.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器和数据传送部件，被配置为执行从存储器传送数据到存储器，并且具有第一模式，以第一位宽度和第二模式传输数据， 第二位宽。 数据传送部分包括：第一锁存电路，被配置为保存从存储器读取的第一数据;第二锁存电路，被配置为保持具有第一模式的第一数据的第一位宽度的第二数据，并且保持第二数据具有第二数据 在第二模式中的第一数据的位宽度，以及将第一锁存电路连接到第二锁存电路并由第一和第二模式共享的数据总线。

公开(公告)号：US20050088870A1

公开(公告)日：2005-04-28

申请号：US10941999

申请日：2004-09-16

申请人： Eiji Kozuka ,  Yasuhiro Suematsu ,  Kazuaki Kawaguchi ,  Mikio Miyata

发明人： Eiji Kozuka ,  Yasuhiro Suematsu ,  Kazuaki Kawaguchi ,  Mikio Miyata

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C11/22

CPC分类号： G11C29/021 ,  G11C29/006 ,  G11C29/02 ,  G11C29/12005

摘要： A semiconductor device that generates a desired internal power supply by using, as a reference potential, a potential obtained by adjusting a preset standard potential, the semiconductor device comprises; a reference potential selection circuit selecting said reference potential on the basis of digital data from among a plurality of potentials of different levels which are obtained by dividing a power supply voltage, and outputting said reference potential in place of said standard potential; a first decision circuit deciding bits of said digital data; a second decision circuit deciding the bits of said digital data, separately from said first decision circuit; and a data transfer circuit transferring to said reference potential selection circuit said digital data which is decided by either one of said first and second decision circuits.

摘要翻译： 一种半导体器件，其通过使用通过调整预设标准电位而获得的电位作为参考电位来产生期望的内部电源，所述半导体器件包括： 参考电位选择电路，其基于通过分割电源电压获得的不同电平的多个电位中的数字数据来选择所述参考电位，并输出所述参考电位代替所述标准电位; 确定所述数字数据的位的第一判定电路; 第二判定电路，与所述第一判定电路分离地决定所述数字数据的位; 以及数据传送电路，传送到所述参考电位选择电路，所述数字数据由所述第一和第二判定电路中的任一个决定。

公开(公告)号：US5691570A

公开(公告)日：1997-11-25

申请号：US719336

申请日：1996-09-25

申请人： Eiji Kozuka

发明人： Eiji Kozuka

IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L21/52 ,  H01L21/82 ,  H01L21/822 ,  H01L23/485 ,  H01L23/50 ,  H01L23/544 ,  H01L27/04 ,  H01L23/48 ,  H01L23/58

CPC分类号： G01R31/2884 ,  H01L22/34 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Normal and reverse IC patterns are each a mirror image of the other. The normal and reverse IC patterns are simultaneously formed on a semiconductor wafer and are simultaneously tested. The wafer with these IC patterns is cut into chips, which are packaged. The normal and reverse IC packages show identical parasitic impedance and uniform performance.

摘要翻译： 正常和反向IC图案各自是另一个的镜像。 正常和反向IC图案同时形成在半导体晶片上并同时测试。 将具有这些IC图案的晶片切成芯片，其被封装。 正常和反向IC封装显示相同的寄生阻抗和均匀的性能。

公开(公告)号：US06680873B2

公开(公告)日：2004-01-20

申请号：US10042937

申请日：2002-01-08

申请人： Kazuyoshi Muraoka ,  Eiji Kozuka

发明人： Kazuyoshi Muraoka ,  Eiji Kozuka

IPC分类号： G11C800

CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C17/18

摘要： The output terminal of a voltage generation circuit is connected to one end portion of a fuse circuit. A transistor is connected to the other end portion of the fuse circuit. In program mode, a voltage generated from the voltage generation circuit is applied to the fuse circuit and a current flows through the fuse circuit and the transistor. In verify mode, a current generated from the voltage generation circuit flows into a pad through a selected fuse circuit and a detection circuit.

摘要翻译： 电压产生电路的输出端连接到熔丝电路的一端。 晶体管连接到熔丝电路的另一端部。 在编程模式中，从电压产生电路产生的电压被施加到熔丝电路，并且电流流过熔丝电路和晶体管。 在验证模式下，从电压产生电路产生的电流通过选定的熔丝电路和检测电路流入焊盘。

公开(公告)号：US5381372A

公开(公告)日：1995-01-10

申请号：US56919

申请日：1993-05-05

申请人： Eiji Kozuka ,  Naokazu Miyawaki

发明人： Eiji Kozuka ,  Naokazu Miyawaki

IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C29/26 ,  G11C29/48 ,  H01L21/66 ,  H01L27/10 ,  G11C29/00

CPC分类号： G11C29/48 ,  G11C29/26

摘要： A semiconductor memory device has a plurality of memory cell arrays; input and output sections each provided so as to correspond to each of the memory cell arrays; and an allocating section provided between the memory cell arrays and the input and output sections, for allocating one of the memory cell arrays to one of the input output sections in ordinary mode, and a plurality of the memory cell arrays to one of the input and output sections in test mode. In the operation test mode, since only a part of the input and output sections are used, it is possible to decrease the number of chips connected to the I/O pins (whose maximum number is limited) of the tester so as to be testable simultaneously, so that the number of chips whose operation tests can be implemented simultaneously can be increased, thus reducing the time required for the operation test of the memory device as a whole.

摘要翻译： 半导体存储器件具有多个存储单元阵列; 每个所述输入和输出部分被提供以对应于每个所述存储单元阵列; 以及设置在所述存储单元阵列与所述输入和输出部分之间的分配部分，用于将所述存储单元阵列中的一个以普通模式分配到所述输入输出部分中的一个，以及将所述多个所述存储单元阵列分配给所述输入和 输出部分在测试模式。 在操作测试模式下，由于仅使用输入和输出部分的一部分，所以可以减少连接到测试仪的I / O引脚（其最大数量受限制）的芯片数量，以便可测试 同时，可以增加同时实现操作测试的芯片的数量，从而减少了整体上存储装置的操作测试所需的时间。

公开(公告)号：US5337286A

公开(公告)日：1994-08-09

申请号：US993854

申请日：1992-12-21

申请人： Osamu Ohto ,  Tomoyuki Hamano ,  Eiji Kozuka ,  Naokazu Miyawaki

发明人： Osamu Ohto ,  Tomoyuki Hamano ,  Eiji Kozuka ,  Naokazu Miyawaki

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C29/00 ,  G11C29/24 ,  G11C29/42 ,  H01L27/10 ,  G11C5/06

CPC分类号： G11C7/1006 ,  G11C29/24 ,  G11C7/10

摘要： A semiconductor memory device is adapted for storing, as a unit of memory information, multiple-bit data constituted by signal data comprised of bit data of 2.sup.n bits (n is a natural number) and remainder data comprised of bit data of C bits (C is a natural number, C

摘要翻译： 一种半导体存储器件适用于存储作为存储器信息的单元，由由2n位（n是自然数）的位数据组成的信号数据构成的多位数据以及由C位（C 是自然数，C <2n）。 该半导体存储器件包括多个电路块，其包括例如由多个存储单元组成的两个存储单元组，以及行解码器和列解码器，适于允许存储单元组内的各个存储单元 有选择地活跃。 因此，行解码器和列解码器变得可操作，使得用作信号数据的位数据被分配给一个或多个电路块一位或多位，并且用作剩余数据的位数据被分配给任何电路 已经进行了位分配的块。

公开(公告)号：US07035158B2

公开(公告)日：2006-04-25

申请号：US10724565

申请日：2003-11-26

申请人： Eiji Kozuka

发明人： Eiji Kozuka

IPC分类号： G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C29/12 ,  G11C29/785 ,  G11C2029/5606

摘要： A fault after an assembling process is saved by using a tester. An error detector circuit compares read data from a memory cell and data from an external input/output terminal by means of a comparator circuit, thereby determining whether a memory cell is good or faulty. The error detector circuit outputs a sense signal COMPERR in the case where the memory cell is faulty. A self fuse program circuit causes a latch circuit LAi to latch an external address as a save address upon receipt of the sense signal COMPERR. By a counter Ci and a switch circuit SW, programming of a save address is carried out by transferring the save address latched at the latch circuit LAi to a fuse program circuit FPi on one bit by one bit basis.

摘要翻译： 使用测试仪保存装配过程后的故障。 误差检测器电路通过比较器电路来比较来自存储器单元的读取数据和来自外部输入/输出端子的数据，从而确定存储器单元是否良好或有故障。 在存储单元故障的情况下，误差检测器电路输出感测信号COMPERR。 自熔丝编程电路使得锁存电路LAi在接收到感测信号COMPERR时将外部地址锁存为存储地址。 通过计数器Ci和开关电路SW，通过将锁存电路LAi上锁存的存储地址一比特地传送到保险丝编程电路FPi来执行存储地址的编程。

公开(公告)号：US06999356B2

公开(公告)日：2006-02-14

申请号：US10941999

申请日：2004-09-16

申请人： Eiji Kozuka ,  Yasuhiro Suematsu ,  Kazuaki Kawaguchi ,  Mikio Miyata

发明人： Eiji Kozuka ,  Yasuhiro Suematsu ,  Kazuaki Kawaguchi ,  Mikio Miyata

IPC分类号： G11C7/14

CPC分类号： G11C29/021 ,  G11C29/006 ,  G11C29/02 ,  G11C29/12005

摘要： A semiconductor device that generates a desired internal power supply by using, as a reference potential, a potential obtained by adjusting a preset standard potential, the semiconductor device comprises; a reference potential selection circuit selecting the reference potential on the basis of digital data from among a plurality of potentials of different levels which are obtained by dividing a power supply voltage, and outputting the reference potential instead of the standard potential; a first decision circuit deciding bits of the digital data; a second decision circuit deciding the bits of the digital data, separately from the first decision circuit; and a data transfer circuit transferring to the reference potential selection circuit the digital data which is decided by either one of the first and second decision circuits.

摘要翻译： 一种半导体器件，其通过使用通过调整预设标准电位而获得的电位作为参考电位来产生期望的内部电源，所述半导体器件包括： 参考电位选择电路，其基于通过划分电源电压获得的不同电平的多个电位中的数字数据，并输出参考电位而不是标准电位来选择参考电位; 确定所述数字数据的位的第一判定电路; 第二判定电路，与第一判定电路分开地决定数字数据的位; 以及数据传送电路，将由第一和第二判定电路中的任一个决定的数字数据传送到参考电位选择电路。

公开(公告)号：US5990729A

公开(公告)日：1999-11-23

申请号：US959774

申请日：1997-10-29

申请人： Eiji Kozuka ,  Masaru Koyanagi

发明人： Eiji Kozuka ,  Masaru Koyanagi

IPC分类号： G11C11/413 ,  G05F1/46 ,  G11C11/407 ,  G05F3/02

CPC分类号： G05F1/465

摘要： A semiconductor integrated circuit can precisely identify the level of an external input signal by stably supplying an internally stepped down voltage. It comprises a first N-channel MOS transistor having its drain/source connected between an external voltage supply node supplied with an external voltage and a first step-down output node for outputting a first stepped down voltage and its gate supplied with a control voltage higher than the external voltage, a first circuit supplied with the first stepped down voltage as operating voltage from the first step-down output node, a second N-channel MOS transistor having its drain/source connected between the external voltage supply node and a second step-down output node for outputting a second stepped down voltage and its gate supplied with the control voltage higher than the external voltage and having a drive capacity different from that of the first N-channel MOS transistor, the second step-down output node being separated from the first step-down output node and a second circuit supplied with the second stepped down voltage as operating voltage from the second step-down output node.

摘要翻译： 半导体集成电路可以通过稳定地提供内部降压来精确地识别外部输入信号的电平。 它包括第一N沟道MOS晶体管，其漏极/源极连接在提供有外部电压的外部电压供应节点和用于输出第一降压电压的第一降压输出节点之间，并且其栅极被提供有较高的控制电压 提供第一降压电压的第一电路作为来自第一降压输出节点的工作电压的第二N沟道MOS晶体管，其漏极/源极连接在外部电压供应节点和第二步骤之间 输出节点，用于输出第二降压电压，其栅极被提供有比外部电压高的控制电压，并具有与第一N沟道MOS晶体管不同的驱动电容，第二降压输出节点被分离 从第一降压输出节点和第二降压电压提供的第二电路作为来自第二降压输出节点的工作电压。

公开(公告)号：US5229846A

公开(公告)日：1993-07-20

申请号：US746026

申请日：1991-08-12

申请人： Eiji Kozuka

发明人： Eiji Kozuka

IPC分类号： H01L23/495 ,  H01L23/50

CPC分类号： H01L23/49503 ,  H01L23/49541 ,  H01L23/50 ,  H01L24/32 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107

摘要： In a semiconductor device including a semiconductor chip, a lead frame with a die pad and plural leads, and a sealing body. The die pad is divided into a plurality of small pieces, and at least one of the plural divided pieces is electrically connected to at least one lead to which a potential is applied. Since the divided die pad is used as a wiring lead, the inductance and resistance of the voltage supply line or the ground line within the chip can be reduced, thus reducing the occurrence of supply voltage and output noise for prevention of erroneous operation.

摘要翻译： 在包括半导体芯片的半导体器件，具有管芯焊盘的引线框架和多个引线以及密封体。 芯片焊盘被分成多个小块，并且多个分割片中的至少一个电连接到施加电位的至少一个引线。 由于使用分割的芯片焊盘作为布线引线，所以能够降低芯片内的电压供给线或地线的电感和电阻，从而减少供电电压和输出噪声的发生，防止误操作。