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    Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device
    1.
    发明授权
    Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device 失效
    数据输入电路，用于减少半导体器件中提取信号与多个数据之间的负载差异

    公开(公告)号：US06734707B2

    公开(公告)日：2004-05-11

    申请号：US10340831

    申请日：2003-01-13

    申请人： Ho-young Song ,  Kyu-hyoun Kim ,  Su-bong Jang

    发明人： Ho-young Song ,  Kyu-hyoun Kim ,  Su-bong Jang

    IPC分类号： H03M700

    CPC分类号： G11C7/1093 ,  G11C7/1072 ,  G11C7/1087 ,  G11C2207/105 ,  G11C2207/108

    摘要： A data input circuit for use in a semiconductor device, the data input circuit reducing a load difference between a fetch signal and a plurality of groups of data. The data input circuit includes first through Nth latching units for latching each one of N groups of data in response to a reference clock, respectively (N is a natural number greater than 2), and a bus for transmitting the reference clock and the N groups of data to the first through Nth latching units. Each of the first through Nth latching units includes a clock buffer for buffering the reference clock; a data buffer for buffering a corresponding group of data of the N groups of data; N−1 dummy elements for respectively receiving each one of the N groups of data, except for the group of data input to the data buffer; and latches for latching data output from the data buffer in synchronization with a signal output from the clock buffer. Use of the data input circuit makes a load on a reference clock the same or substantially the same as that on each group of data. Therefore, a load difference between the reference clock and each group of data is reduced to reduce a skew therebetween.

    摘要翻译： 一种用于半导体器件的数据输入电路，所述数据输入电路减小了获取信号与多组数据之间的负载差异。 数据输入电路包括第一到第N个锁存单元，用于分别响应于参考时钟（N是大于2的自然数）来锁存N组数据中的每一个，以及用于发送参考时钟和 N组数据到第一至第N个锁存单元。 每个第一至第N个锁存单元包括用于缓冲参考时钟的时钟缓冲器; 数据缓冲器，用于缓冲N组数据的相应的数据组; N-1个虚拟元素，用于分别接收N组数据中的每一个，除了输入到数据缓冲器的数据组之外; 以及用于锁存从数据缓冲器输出的数据与从时钟缓冲器输出的信号同步的锁存器。 使用数据输入电路使参考时钟上的负载与每组数据上的相同或基本相同。 因此，参考时钟与每组数据之间的负载差减小，以减少它们之间的偏斜。

    Digital phase detector with zero phase offset
    2.
    发明授权
    Digital phase detector with zero phase offset 失效

    公开(公告)号：US08718216B2

    公开(公告)日：2014-05-06

    申请号：US13242053

    申请日：2011-09-23

    申请人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

    发明人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0037 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/089

    摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

    Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device
    3.
    发明授权
    Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device 失效
    通过向DRAM设备发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理

    公开(公告)号：US08639874B2

    公开(公告)日：2014-01-28

    申请号：US12341515

    申请日：2008-12-22

    申请人： Warren Edward Maule ,  Kevin C. Gower ,  Kyu-hyoun Kim ,  Dustin James VanStee

    发明人： Warren Edward Maule ,  Kevin C. Gower ,  Kyu-hyoun Kim ,  Dustin James VanStee

    IPC分类号： G06F12/06

    CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C11/4074

    摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

    摘要翻译： 一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级 在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。 通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态， 并激活用于将存储器单元作为正常的有源或备用设备读/写。

    MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE
    6.
    发明申请
    MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE 有权
    具有可编程刷新周期的存储器系统

    公开(公告)号：US20120151131A1

    公开(公告)日：2012-06-14

    申请号：US12963797

    申请日：2010-12-09

    申请人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

    发明人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

    IPC分类号： G06F12/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4065

    摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

    摘要翻译： 一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。 刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。 响应于接收刷新命令刷新的存储器单元的数量是可编程的。

    Computer system wafer integrating different dies in stacked master-slave structures
    7.
    发明申请
    Computer system wafer integrating different dies in stacked master-slave structures 审中-公开
    在堆叠的主从结构中集成不同模具的计算机系统晶片

    公开(公告)号：US20110272788A1

    公开(公告)日：2011-11-10

    申请号：US12777177

    申请日：2010-05-10

    申请人： Kyu-hyoun Kim ,  Paul Coteus

    发明人： Kyu-hyoun Kim ,  Paul Coteus

    IPC分类号： H01L29/06 ,  H01L21/00

    CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

    摘要： A stacked 3D integrated circuit structure is manufactured with a common image design for dies which allows diced master dies to cut from the common wafer and diced slave dies cut to be cut from a wafer which has the common image design. In an embodiment is stacked to form a wafer-to-wafer 3D stack before dicing. Master and slave elements which are used for only one kind of separated individual integrated circuit dies which are located along die edges and at die centers before dicing separation of individual integrated circuit chips. A master wafer is shifted ½ way across a die to make cutting along a kerf line effective to provide both master and slave dies. Multiple slaves can be stacked and coupled to a master die which acts as a bus master when attached to a bus to which only the master die is directly connected. The use of a common wafer design minimizes cost of manufacture of chips destined to be stacked as 3D integrated circuits.

    摘要翻译： 制造堆叠的3D集成电路结构，其具有用于管芯的公共图像设计，其允许切割的主管芯从公共晶片切割并切割成具有共同图像设计的晶片切割的切割从属裸片。 在一个实施例中，在切割之前堆叠以形成晶片到晶片3D堆叠。 主单元和从元件仅用于单个集成电路芯片切割分离之前沿着芯片边缘和模具中心位置的一种分离的单独集成电路管芯。 主晶片沿模具移动1/2路，以便沿着切割线进行切割有效地提供主模和从模。 多个从器件可以堆叠并耦合到主引脚，当连接到仅母模直接连接的总线时，主器件用作总线主器件。 使用普通晶圆设计可最大限度地降低作为3D集成电路堆叠的芯片的制造成本。

    MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR READ TIMING CALIBRATION
    8.
    发明申请
    MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR READ TIMING CALIBRATION 有权
    具有扩展STROBE BURST的存储接口进行读取时序校准

    公开(公告)号：US20110225445A1

    公开(公告)日：2011-09-15

    申请号：US12723885

    申请日：2010-03-15

    申请人： Kevin C. Gower ,  Kyu-hyoun Kim

    发明人： Kevin C. Gower ,  Kyu-hyoun Kim

    IPC分类号： G06F12/00 ,  G06F1/04

    CPC分类号： G06F1/04 ,  G06F12/00 ,  G06F13/161 ,  G06F13/1689

    摘要： Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the read latency and/or the latency window of a memory controller such that a data signal and a data strobe signal are received by the memory controller within the latency window of the memory controller.

    摘要翻译： 用于校准控制器和存储器件之间通信的参数的方法和系统。 存储器控制器可以被配置为校准存储器控制器的读延迟和/或等待时间窗口中的一个或多个，使得存储器控制器在存储器控制器的延迟窗口内接收数据信号和数据选通信号。

    MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR WRITE TIMING CALIBRATION
    9.
    发明申请
    MEMORY INTERFACE HAVING EXTENDED STROBE BURST FOR WRITE TIMING CALIBRATION 有权
    具有扩展STRBE BURST的存储接口进行写时序校准

    公开(公告)号：US20110225444A1

    公开(公告)日：2011-09-15

    申请号：US12723843

    申请日：2010-03-15

    申请人： Kevin C. Gower ,  Kyu-hyoun Kim

    发明人： Kevin C. Gower ,  Kyu-hyoun Kim

    IPC分类号： G06F12/00 ,  G06F1/04

    CPC分类号： G06F1/04 ,  G06F13/1694 ,  G11C7/1093 ,  G11C2207/2254

    摘要： Methods and systems for calibrating parameters for communication between a controller and a memory device. A memory controller may be configured to calibrate one or more of the write latency and/or the latency window of a memory device such that a data signal and a data strobe signal are received by the memory device within the latency window of the memory device.

    摘要翻译： 用于校准控制器和存储器件之间通信的参数的方法和系统。 存储器控制器可以被配置为校准存储器件的写延迟和/或等待时间窗口中的一个或多个，使得数据信号和数据选通信号在存储器件的延迟窗口内由存储器件接收。

    Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device
    10.
    发明申请
    Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device 失效
    通过向DRAM器件发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理

    公开(公告)号：US20100162020A1

    公开(公告)日：2010-06-24

    申请号：US12341515

    申请日：2008-12-22

    申请人： Warren Edward Maule ,  Kevin C. Gower ,  Kyu-hyoun Kim ,  Dustin James VanStee

    发明人： Warren Edward Maule ,  Kevin C. Gower ,  Kyu-hyoun Kim ,  Dustin James VanStee

    IPC分类号： G06F1/32 ,  G06F12/06

    CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C11/4074

    摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

    摘要翻译： 一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级 在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。 通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态， 并激活用于将存储器单元作为正常的有源或备用设备读/写。