公开(公告)号：US20110220990A1

公开(公告)日：2011-09-15

申请号：US12722384

申请日：2010-03-11

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

摘要翻译： 一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。 沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。 使用第二掩模形成由中间介电区分隔的第一和第二导电区域。 使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。 使用第四掩模形成与栅极金属区域的接触。 半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

公开(公告)号：US20130228860A1

公开(公告)日：2013-09-05

申请号：US13865941

申请日：2013-04-18

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

公开(公告)号：US08994101B2

公开(公告)日：2015-03-31

申请号：US13865941

申请日：2013-04-18

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L27/088 ,  H01L21/283 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/732 ,  H01L29/423 ,  H01L21/265 ,  H01L29/45 ,  H01L29/49 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

摘要翻译： 一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。 沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。 使用第二掩模形成由中间介电区分隔的第一和第二导电区域。 使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。 使用第四掩模形成与栅极金属区域的接触。 半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

公开(公告)号：US08431457B2

公开(公告)日：2013-04-30

申请号：US12722384

申请日：2010-03-11

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L21/027 ,  H01L29/78

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

摘要翻译： 一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。 沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。 使用第二掩模形成由中间介电区分隔的第一和第二导电区域。 使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。 使用第四掩模形成与栅极金属区域的接触。 半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

公开(公告)号：US08580676B2

公开(公告)日：2013-11-12

申请号：US13361486

申请日：2012-01-30

申请人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

发明人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

IPC分类号： H01L21/4763

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

摘要翻译： 形成在半导体衬底上的半导体器件可以包括形成在位于活性单元区域中的接触沟槽中的部件。 该部件可以包括沉积在接触沟槽的底部和侧壁的一部分上的阻挡金属和沉积在接触沟槽的剩余部分中的钨丝塞。 阻挡金属可以包括第一和第二金属层。 第一金属层可以靠近接触沟槽的侧壁和底部。 第一金属层可以包括氮化物。 第二金属层可以在第一金属层和钨插塞之间以及钨插塞和侧壁之间。 第二金属层覆盖未被第一金属层覆盖的侧壁的部分。

公开(公告)号：US20120129328A1

公开(公告)日：2012-05-24

申请号：US13361486

申请日：2012-01-30

申请人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

发明人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

IPC分类号： H01L21/329 ,  H01L21/768

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

摘要翻译： 形成在半导体衬底上的半导体器件可以包括形成在位于活性单元区域中的接触沟槽中的部件。 该部件可以包括沉积在接触沟槽的底部和侧壁的一部分上的阻挡金属和沉积在接触沟槽的剩余部分中的钨丝塞。 阻挡金属可以包括第一和第二金属层。 第一金属层可以靠近接触沟槽的侧壁和底部。 第一金属层可以包括氮化物。 第二金属层可以在第一金属层和钨插塞之间以及钨插塞和侧壁之间。 第二金属层覆盖未被第一金属层覆盖的侧壁的部分。

公开(公告)号：US08138605B2

公开(公告)日：2012-03-20

申请号：US12606005

申请日：2009-10-26

申请人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

发明人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/148 ,  H01L29/768 ,  H01L27/095

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

摘要翻译： 形成在半导体衬底上的半导体器件可以包括形成在位于活性单元区域中的接触沟槽中的部件。 该部件可以包括沉积在接触沟槽的底部和侧壁的一部分上的阻挡金属和沉积在接触沟槽的剩余部分中的钨丝塞。 阻挡金属可以包括第一和第二金属层。 第一金属层可以靠近接触沟槽的侧壁和底部。 第一金属层可以包括氮化物。 第二金属层可以在第一金属层和钨插塞之间以及钨插塞和侧壁之间。 第二金属层覆盖未被第一金属层覆盖的侧壁的部分。

公开(公告)号：US20110095361A1

公开(公告)日：2011-04-28

申请号：US12606005

申请日：2009-10-26

申请人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

发明人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

IPC分类号： H01L27/06 ,  H01L21/329 ,  H01L29/872

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

摘要翻译： 形成在半导体衬底上的半导体器件可以包括形成在位于活性单元区域中的接触沟槽中的部件。 该部件可以包括沉积在接触沟槽的底部和侧壁的一部分上的阻挡金属和沉积在接触沟槽的剩余部分中的钨丝塞。 阻挡金属可以包括第一和第二金属层。 第一金属层可以靠近接触沟槽的侧壁和底部。 第一金属层可以包括氮化物。 第二金属层可以在第一金属层和钨插塞之间以及钨插塞和侧壁之间。 第二金属层覆盖未被第一金属层覆盖的侧壁的部分。

公开(公告)号：US20120205737A1

公开(公告)日：2012-08-16

申请号：US13456406

申请日：2012-04-26

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

摘要翻译： 半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。

公开(公告)号：US08193580B2

公开(公告)日：2012-06-05

申请号：US12583191

申请日：2009-08-14

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

摘要翻译： 半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。 非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。 另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。 源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。 另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。