公开(公告)号：US08431457B2

公开(公告)日：2013-04-30

申请号：US12722384

申请日：2010-03-11

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L21/027 ,  H01L29/78

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

摘要翻译： 一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。 沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。 使用第二掩模形成由中间介电区分隔的第一和第二导电区域。 使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。 使用第四掩模形成与栅极金属区域的接触。 半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

公开(公告)号：US20130228860A1

公开(公告)日：2013-09-05

申请号：US13865941

申请日：2013-04-18

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

公开(公告)号：US20110220990A1

公开(公告)日：2011-09-15

申请号：US12722384

申请日：2010-03-11

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

摘要翻译： 一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。 沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。 使用第二掩模形成由中间介电区分隔的第一和第二导电区域。 使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。 使用第四掩模形成与栅极金属区域的接触。 半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

公开(公告)号：US08994101B2

公开(公告)日：2015-03-31

申请号：US13865941

申请日：2013-04-18

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L27/088 ,  H01L21/283 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/732 ,  H01L29/423 ,  H01L21/265 ,  H01L29/45 ,  H01L29/49 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

摘要翻译： 一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。 沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。 使用第二掩模形成由中间介电区分隔的第一和第二导电区域。 使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。 使用第四掩模形成与栅极金属区域的接触。 半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

公开(公告)号：US08502302B2

公开(公告)日：2013-08-06

申请号：US13098852

申请日：2011-05-02

申请人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Hong Chang ,  Jongoh Kim ,  John Chen

发明人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Hong Chang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L29/7801 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0891 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/872

摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

摘要翻译： 半导体器件包括多个沟槽，包括有源区域中的有源栅极沟槽和栅极流道/终止沟槽以及在有源区域外部的终止区域中的屏蔽电极拾取沟槽。 栅极流道/终止沟槽包括限定位于有源区域之外的台面的一个或多个沟槽。 在多个沟槽中形成第一导电区域。 在限定台面的沟槽中形成中间介质区域和端接保护区域。 在限定台面的沟槽部分中形成第二导电区域。 第二导电区域通过中间介电区域与第一导电区域电隔离。 对第二导电区域进行第一电接触，并且在屏蔽电极拾取沟槽中对第一导电区域进行第二电接触。 在台面内形成一个或多个肖特基二极管。

公开(公告)号：US20120280307A1

公开(公告)日：2012-11-08

申请号：US13098852

申请日：2011-05-02

申请人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Hong Chang ,  Jongoh Kim ,  John Chen

发明人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Hong Chang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L29/7801 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0891 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/872

摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

摘要翻译： 半导体器件包括多个沟槽，包括有源区域中的有源栅极沟槽和栅极流道/终止沟槽以及在有源区域外部的终止区域中的屏蔽电极拾取沟槽。 栅极流道/终止沟槽包括限定位于有源区域之外的台面的一个或多个沟槽。 在多个沟槽中形成第一导电区域。 在限定台面的沟槽中形成中间介质区域和端接保护区域。 在限定台面的沟槽部分中形成第二导电区域。 第二导电区域通过中间介电区域与第一导电区域电隔离。 对第二导电区域进行第一电接触，并且在屏蔽电极拾取沟槽中对第一导电区域进行第二电接触。 在台面内形成一个或多个肖特基二极管。

公开(公告)号：US20130075808A1

公开(公告)日：2013-03-28

申请号：US13241126

申请日：2011-09-22

申请人： Daniel Calafut ,  Yi Su ,  Jongoh Kim ,  Hong Chang ,  Hamza Yilmaz ,  Daniel S. Ng

发明人： Daniel Calafut ,  Yi Su ,  Jongoh Kim ,  Hong Chang ,  Hamza Yilmaz ,  Daniel S. Ng

IPC分类号： H01L29/872 ,  H01L27/06

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/06 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/872

摘要： A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.

摘要翻译： 肖特基二极管包括形成在半导体衬底上的半导体层; 第一和第二沟槽形成在半导体层中，其中第一和第二沟槽衬有薄介电层，并部分地填充有沟槽导体层，并且第一和第二沟槽的剩余部分填充有第一介电层; 以及形成在所述第一沟槽和所述第二沟槽之间的所述半导体层的顶表面上的肖特金属层。 肖特基二极管由肖特基金属层作为阳极形成，第一和第二沟槽之间的半导体层作为阴极形成。 第一和第二沟槽中的每一个中的沟槽导体层电连接到肖特基二极管的阳极。 在一个实施例中，肖特基二极管与同一半导体衬底上的沟槽场效应晶体管集成。

公开(公告)号：US08610235B2

公开(公告)日：2013-12-17

申请号：US13241126

申请日：2011-09-22

申请人： Daniel Calafut ,  Yi Su ,  Jongoh Kim ,  Hong Chang ,  Hamza Yilmaz ,  Daniel S. Ng

发明人： Daniel Calafut ,  Yi Su ,  Jongoh Kim ,  Hong Chang ,  Hamza Yilmaz ,  Daniel S. Ng

IPC分类号： H01L29/47

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/06 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/872

摘要： A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.

摘要翻译： 肖特基二极管包括形成在半导体衬底上的半导体层; 第一和第二沟槽形成在半导体层中，其中第一和第二沟槽衬有薄介电层，并部分地填充有沟槽导体层，并且第一和第二沟槽的剩余部分填充有第一介电层; 以及形成在所述第一沟槽和所述第二沟槽之间的所述半导体层的顶表面上的肖特金属层。 肖特基二极管由肖特基金属层作为阳极形成，第一和第二沟槽之间的半导体层作为阴极形成。 第一和第二沟槽中的每一个中的沟槽导体层电连接到肖特基二极管的阳极。 在一个实施例中，肖特基二极管与同一半导体衬底上的沟槽场效应晶体管集成。

公开(公告)号：US09257375B2

公开(公告)日：2016-02-09

申请号：US13236931

申请日：2011-09-20

申请人： Anup Bhalla ,  Yi Su ,  David Grey

发明人： Anup Bhalla ,  Yi Su ,  David Grey

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/074 ,  H01L23/3171 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/50 ,  H01L29/7827 ,  H01L2224/02166 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/30101 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.

摘要翻译： 多管芯封装具有多个引线，第一和第二半导体管芯叠加并结合在一起，形成管芯堆叠。 管芯堆叠具有相对的第一和第二面，其中第一和第二半导体管芯中的每一个具有栅极，漏极和源极区以及栅极，漏极和源极接触。 第一相对侧具有与第一组多个引线电连通的第二半导体管芯的漏极接触。 第一半导体管芯的栅极，漏极和源极接触以及第二半导体管芯的栅极和源极触点设置在所述相对侧的第二侧上并且与第二组多个引线电连通。 用于第一半导体管芯的源极的引线可以与第二半导体管芯的漏极引线相同。

公开(公告)号：US20140151790A1

公开(公告)日：2014-06-05

申请号：US13873017

申请日：2013-04-29

申请人： Sik Lui ,  Yi Su ,  Daniel Ng ,  Anup Bhalla

发明人： Sik Lui ,  Yi Su ,  Daniel Ng ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7806 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

摘要翻译： 集成结构结合了场效应晶体管和肖特基二极管。 形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。 每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。 每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。 衬底组合物的暴露部分分离身体区域。 每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。 每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。