公开(公告)号：US06320473B1

公开(公告)日：2001-11-20

申请号：US09409494

申请日：1999-09-30

申请人： Horst Leuschner

发明人： Horst Leuschner

IPC分类号： H03B536

CPC分类号： H03B5/36 ,  H03B5/06

摘要： The present invention relates to oscillator circuits for providing periodic signals. The oscillator circuit includes a crystal element having a high Q value and good stability. A high-gain amplifier is used with the crystal element to produce an oscillating signal. The oscillator is further configured to include an input protection circuit for reducing the effects of undesirably high input voltage levels, and a coupling capacitor to reduce leakage between the amplifier and the input protection circuit. A high output signal level is provided to a Schmidtt trigger amplifier through configuring the output to be taken from the input of the high-gain amplifier.

摘要翻译： 本发明涉及用于提供周期性信号的振荡器电路。 振荡电路包括具有高Q值和良好稳定性的晶体元件。 使用高增益放大器与晶体元件产生振荡信号。 振荡器还被配置为包括用于减少不期望的高输入电压电平的影响的输入保护电路，以及用于减小放大器与输入保护电路之间的泄漏的耦合电容器。 通过配置从高增益放大器的输入获取的输出，向Schmidtt触发放大器提供高输出信号电平。

公开(公告)号：US4459497A

公开(公告)日：1984-07-10

申请号：US342040

申请日：1982-01-25

申请人： Clinton C. K. Kuo ,  Horst Leuschner

发明人： Clinton C. K. Kuo ,  Horst Leuschner

IPC分类号： G11C11/419 ,  H03K5/02 ,  H03K5/24 ,  G11C7/06

CPC分类号： H03K5/023

摘要： A sense amplifier quickly charges a column line to a first predetermined voltage level with first, second and third transistors and then charges the column to a second predetermined voltage by using only the second and third transistors. The second and third transistors continue charging to the second predetermined voltage by virtue of having a lower threshold voltage than the first transistor. If a selected memory cell in the column is in a conducting state, the column charges to only the first predetermined voltage for detection as a logic "0". If the selected memory cell in the column is in a non-conducting state, the column continues charging to the second predetermined voltage for detection as a logic "1".

摘要翻译： 读出放大器利用第一，第二和第三晶体管将列线快速充电到第一预定电压电平，然后仅使用第二和第三晶体管将该列充电至第二预定电压。 由于具有比第一晶体管低的阈值电压，第二和第三晶体管继续充电到第二预定电压。 如果列中选定的存储单元处于导通状态，则该列仅将第一预定电压充电至逻辑“0”。 如果列中所选择的存储单元处于非导通状态，则列继续充电到第二预定电压以作为逻辑“1”。

公开(公告)号：US4065916A

公开(公告)日：1978-01-03

申请号：US759696

申请日：1977-01-17

申请人： Horst Leuschner

发明人： Horst Leuschner

IPC分类号： G04G5/00 ,  G04G5/04 ,  G04G19/02 ,  G04G19/12 ,  G04C3/00 ,  G04B19/00

CPC分类号： G04G19/12 ,  G04G5/04

摘要： An electronic timepiece includes a shutdown latch circuit. The latch circuit is initially set by insertion of a battery power source in the electronic timepiece. When the latch circuit is set, all other circuits in the timepiece, and particularly the display circuits, are turned off to conserve battery power during the "shelf-life" of the electronic timepiece. When the command switch is first activated, the latch circuit is reset, and all of the other electronic circuits are turned on in a predetermined initialized condition.

摘要翻译： 电子钟表包括关闭锁存电路。 最初通过在电子表中插入电池电源来设定闩锁电路。 当锁存电路被设置时，钟表中的所有其他电路，特别是显示电路都被关闭，以在电子表的“保存期限”期间节省电池电力。 当命令开关首先被激活时，锁存电路被复位，并且所有其它电子电路在预定的初始化状态下被接通。

公开(公告)号：US4755750A

公开(公告)日：1988-07-05

申请号：US32995

申请日：1987-04-02

申请人： Horst Leuschner

发明人： Horst Leuschner

IPC分类号： G01R31/00 ,  G01R35/00 ,  G01B11/00

CPC分类号： G01R31/00 ,  G01R35/005

摘要： The invention comprises a system of alignment key patterns, within the scribe lines of a semiconductor chip, which allow more accurate placement of wafer probes, and more accurate location of fuses for the purposes of blowing selected ones of those fuses by means of laser energy.

摘要翻译： 本发明包括在半导体芯片的划线内的对准键图案的系统，其允许晶片探针的更准确的放置，以及用于通过激光能量吹送这些熔丝中的选定的熔丝的更准确的熔丝位置。

公开(公告)号：US4685083A

公开(公告)日：1987-08-04

申请号：US783493

申请日：1985-10-03

申请人： Horst Leuschner

发明人： Horst Leuschner

IPC分类号： G11C17/00 ,  G11C11/00 ,  G11C14/00 ,  G11C16/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30 ,  G11C11/40

CPC分类号： G11C16/30 ,  G11C14/00 ,  G11C16/10

摘要： An improved nonvolatile memory has an adaptive system to regulate the charging current supplied to store data on nonvolatile storage nodes in order to provide acceptability low strain on the tunnel oxide and to compensate for process variations and change in the Fowler-Nordheim tunnel oxide transport characteristics caused by electron trapping over time.

摘要翻译： 改进的非易失性存储器具有自适应系统，以调节提供以在非易失性存储节点上存储数据的充电电流，以便在隧道氧化物上提供可接受的低应变，并补偿由于引起的Fowler-Nordheim隧道氧化物传输特性的过程变化和变化 通过电子俘获随着时间的推移。

公开(公告)号：US4287439A

公开(公告)日：1981-09-01

申请号：US034513

申请日：1979-04-30

申请人： Horst Leuschner

发明人： Horst Leuschner

IPC分类号： G05F3/30 ,  H01L31/00

CPC分类号： G05F3/30

摘要： A bandgap voltage reference source is provided which is temperature stable or temperature controlled and can be made by standard CMOS process. The reference has two substrate bipolar transistors with the emitter current density of one of the transistors being larger than the emitter current density of the other transistor. The transistors are used as emitter followers having resistors in their emitter circuits from which an error voltage is obtained. The error voltage is amplified through a differential or operational amplifier. Through the amplifier or through a resistor network, an output voltage higher or lower, respectively, than the bandgap voltage can be obtained. The output voltage can be made to have a positive, negative, or zero temperature coefficient.

摘要翻译： 提供了温度稳定或温度控制的带隙电压参考源，可以通过标准CMOS工艺制造。 该参考具有两个基板双极晶体管，其中一个晶体管的发射极电流密度大于另一个晶体管的发射极电流密度。 晶体管用作其发射极电路中具有电阻器的发射极跟随器，从其获得误差电压。 误差电压通过差分或运算放大器放大。 通过放大器或通过电阻网络，可以获得比带隙电压更高或更低的输出电压。 可以使输出电压具有正，负或零温度系数。

公开(公告)号：US4052701A

公开(公告)日：1977-10-04

申请号：US681882

申请日：1976-04-30

申请人： Horst Leuschner

发明人： Horst Leuschner

IPC分类号： G08C19/12 ,  H04Q9/12

CPC分类号： G08C19/12

摘要： Ultrasonic remote control receiver wherein reference frequency pulses are counted during a counting cycle comprising a predetermined number of received command signals, each command signal occupying a different frequency channel. At the end of each counting cycle, the reference frequency count is compared with the count during the preceding counting cycle. A validated output from the receiver occurs only after a predetermined number of uninterrupted identical comparisons have occurred. Interference with a validated output signal by spurious received signals e.g. noise signals is minimized by providing for invalidation of an output signal only after a predetermined number of uninterrupted non-identical count comparisons. Two of the receiver outputs are used to generate a variable duty cycle pulse train, one output increasing and the other decreasing the duty cycle. A receiver is disclosed in the context of a TV broadcast receiver wherein the variable level d.c. control signal is used to control an electronic sound attenuator. The remote control receiver also includes power-on-reset and mute functions. Each of the remote control receiver outputs has a parallel connected manual switch, to some of which anti-bounce circuits are connected.

公开(公告)号：US5514612A

公开(公告)日：1996-05-07

申请号：US282033

申请日：1994-07-28

申请人： Bhasker Rao ,  Horst Leuschner ,  Ashok Chalaka

发明人： Bhasker Rao ,  Horst Leuschner ,  Ashok Chalaka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/47 ,  H01L29/872 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/0248 ,  H01L27/0251 ,  H01L27/0259

摘要： A semiconductor device which has a resistor, a capacitor, a Schottky diode, and an ESD protection device all formed on a single semiconductor substrate. The resistor and the capacitor are coupled together in series. The Schottky diode and the ESD protection device are coupled in parallel to the series connection of the resistor and capacitor.

摘要翻译： 具有电阻器，电容器，肖特基二极管和ESD保护器件的半导体器件全部形成在单个半导体衬底上。 电阻器和电容器串联在一起。 肖特基二极管和ESD保护器件与电阻器和电容器的串联连接并联。

公开(公告)号：US5355014A

公开(公告)日：1994-10-11

申请号：US25600

申请日：1993-03-03

申请人： Bhasker Rao ,  Horst Leuschner ,  Ashok Chalaka

发明人： Bhasker Rao ,  Horst Leuschner ,  Ashok Chalaka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/47 ,  H01L29/872 ,  H01L27/06 ,  H01L29/08 ,  H01L29/48

CPC分类号： H01L27/0251 ,  H01L27/0248 ,  H01L27/0259

摘要： A semiconductor device which has a resistor, a capacitor, and a Schottky diode all formed on a single semiconductor substrate. The capacitor comprises a dielectric region between two metal regions. The resistor comprises an N.sup.+ -type well. The Schottky diode comprises an N-type tub, a metal region in contact with the tub, and an N.sup.+ -type region formed in the N-type tub. The resistor and capacitor are coupled by a metal region which contacts one of the metal regions of the capacitor and the N.sup.+ -type well of the resistor. The resistor and Schottky diode are coupled by a metal region which contacts the N.sup.+ -type well of the resistor and the N.sup.+ -type well of the Schottky diode.

摘要翻译： 具有电阻器，电容器和肖特基二极管的半导体器件全部形成在单个半导体衬底上。 电容器包括两个金属区域之间的电介质区域。 电阻器包括N +型阱。 肖特基二极管包括N型桶，与桶接触的金属区域和形成在N型桶中的N +型区域。 电阻器和电容器通过接触电容器的金属区域和电阻器的N +型阱之一的金属区域耦合。 电阻器和肖特基二极管通过接触电阻器的N +型阱和肖特基二极管的N +型阱的金属区域耦合。

公开(公告)号：US4510584A

公开(公告)日：1985-04-09

申请号：US454418

申请日：1982-12-29

申请人： Donald R. Dias ,  Daniel C. Guterman ,  Robert J. Proebsting ,  Horst Leuschner

发明人： Donald R. Dias ,  Daniel C. Guterman ,  Robert J. Proebsting ,  Horst Leuschner

IPC分类号： G11C14/00 ,  G11C11/40

CPC分类号： G11C14/00

摘要： A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit. If a positive charge state has been stored at the charge storage node (44) the transistor (42) is rendered conductive to pull the DATA node (22) to ground to restore the data state to the volatile memory circuit. If a negative charge state has been stored at the charge storage node (44) there is no load applied to either the DATA node (20) or the DATA node (22). The cross-couple transistors, (12,14) are fabricated to have different lengths such that the node (22) is driven to a high voltage state whenever a default condition is encountered, thereby restoring the original data state to the volatile memory circuit.

摘要翻译： 非易失性随机存取存储器单元（10）包括静态随机存取存储器电路和相应的非易失性存储器电路。 易失性存储器电路以常规方式工作并具有第一和第二数据状态。 在接收到存储命令信号时，根据易失性存储器电路中的数据状态，电荷存储节点被驱动到第一或第二充电状态。 对于一个充电状态，电荷存储信号通过晶体管（64）和电容器（68）被选通到浮动栅极节点（44）。 电荷通过包括在单晶衬底上制造的电介质的电流隧穿元件（48,50）传送到浮栅节点（44）。 对于调用操作，将调用命令信号施加到将晶体管（42）耦合到易失性存储器电路的＆amp; D＆D节点（22）的晶体管（52）。 如果正电荷状态已经存储在电荷存储节点（44）处，晶体管（42）被导通以将＆amp;上升＆D节点（22）拉到地，以将数据状态恢复到易失性存储器电路。 如果在电荷存储节点（44）处存储了负电荷状态，则没有负载施加到DATA节点（20）或者＆amp; Upbar＆D节点（22）上。 交叉耦合晶体管（12,14）被制造成具有不同的长度，使得每当遇到默认条件时，节点（22）被驱动到高电压状态，从而将原始数据状态恢复到易失性存储器电路。