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    Post ECP multi-step anneal/H2 treatment to reduce film impurity
    3.
    发明授权
    Post ECP multi-step anneal/H2 treatment to reduce film impurity 有权
    后期ECP多步退火/ H2处理以降低膜杂质

    公开(公告)号：US07432192B2

    公开(公告)日：2008-10-07

    申请号：US11347946

    申请日：2006-02-06

    申请人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

    发明人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L21/2885

    摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

    摘要翻译： 描述了在双镶嵌方案中形成铜互连的方法。 在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。 进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。 使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积 第二铜层超过沟槽。 在第二退火步骤之后，CMP工艺使铜层平坦化。 通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。

    Post ECP multi-step anneal/H2 treatment to reduce film impurity
    5.
    发明授权
    Post ECP multi-step anneal/H2 treatment to reduce film impurity 失效
    后期ECP多步退火/ H2处理以降低膜杂质

    公开(公告)号：US07030016B2

    公开(公告)日：2006-04-18

    申请号：US10812729

    申请日：2004-03-30

    申请人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

    发明人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/2885

    摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

    摘要翻译： 描述了在双镶嵌方案中形成铜互连的方法。 在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。 进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。 使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积 第二铜层 - 过度填充沟槽。 在第二退火步骤之后，CMP工艺使铜层平坦化。 通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。

    Post ECP multi-step anneal/H2 treatment to reduce film impurity
    6.
    发明申请
    Post ECP multi-step anneal/H2 treatment to reduce film impurity 失效
    后期ECP多步退火/ H2处理以降低膜杂质

    公开(公告)号：US20050227479A1

    公开(公告)日：2005-10-13

    申请号：US10812729

    申请日：2004-03-30

    申请人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

    发明人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

    IPC分类号： H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/2885

    摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

    摘要翻译： 描述了在双镶嵌方案中形成铜互连的方法。 在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。 进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。 使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积 第二铜层 - 过度填充沟槽。 在第二退火步骤之后，CMP工艺使铜层平坦化。 通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。

    Post ECP multi-step anneal/H2 treatment to reduce film impurity
    7.
    发明申请
    Post ECP multi-step anneal/H2 treatment to reduce film impurity 有权
    后期ECP多步退火/ H2处理以降低膜杂质

    公开(公告)号：US20060216930A1

    公开(公告)日：2006-09-28

    申请号：US11347946

    申请日：2006-02-06

    申请人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

    发明人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L21/2885

    摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

    摘要翻译： 描述了在双镶嵌方案中形成铜互连的方法。 在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。 进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。 使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积 第二铜层超过沟槽。 在第二退火步骤之后，CMP工艺使铜层平坦化。 通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。

    Method of reducing the pattern effect in the CMP process
    8.
    发明授权
    Method of reducing the pattern effect in the CMP process 有权
    降低CMP工艺中图案效果的方法

    公开(公告)号：US07183199B2

    公开(公告)日：2007-02-27

    申请号：US10724201

    申请日：2003-12-01

    申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

    发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/3212 ,  H01L21/7684

    摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

    摘要翻译： 降低CMP工艺中图案效果的方法。 该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。 还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

    Method of reducing the pattern effect in the CMP process
    9.
    发明申请
    Method of reducing the pattern effect in the CMP process 有权
    降低CMP工艺中图案效果的方法

    公开(公告)号：US20050118808A1

    公开(公告)日：2005-06-02

    申请号：US10724201

    申请日：2003-12-01

    申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

    发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

    IPC分类号： H01L21/302 ,  H01L21/321 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/3212 ,  H01L21/7684

    摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

    摘要翻译： 降低CMP工艺中图案效果的方法。 该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。 还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

    Method for preventing voids in metal interconnects
    10.
    发明授权
    Method for preventing voids in metal interconnects 有权
    防止金属互连中空隙的方法

    公开(公告)号：US07122471B2

    公开(公告)日：2006-10-17

    申请号：US10835315

    申请日：2004-04-28

    申请人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

    发明人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

    IPC分类号： H01L21/44 ,  H01L21/42 ,  H01L21/268 ,  H01L21/428

    CPC分类号： H01L21/68728 ,  H01L21/67109 ,  H01L21/68707 ,  H01L21/76877

    摘要： A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

    摘要翻译： 公开了一种用于防止在晶片上制造的金属互连中空隙形成的新方法，特别是在热退火工艺期间。 该方法包括在晶片上的金属线之间制造金属互连。 在进行用于降低互连的电阻的热退火工艺期间，晶片以与晶片加热器隔开的关系定位。 这种间隔结构通过减少加热的空气或气体抵靠和晶片背面的颗粒的存在而提高晶片加热的稳定性和均匀性。 这在退火过程中消除或至少基本上减少了互连件中空隙的形成。