公开(公告)号：US06858532B2

公开(公告)日：2005-02-22

申请号：US10316211

申请日：2002-12-10

申请人： Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

发明人： Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/732 ,  H01L21/4763

CPC分类号： H01L29/66242 ,  H01L21/31116 ,  H01L21/8249

摘要： An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

摘要翻译： 描述了氧化物蚀刻工艺，其可用于双极SiGe器件中的发射极和基极准备。 所采用的低温工艺通过保留绝缘TEOS玻璃的COR蚀刻产生发射极和基极之间的电绝缘。 绝缘TEOS玻璃提供降低的电容并有助于实现高速度。 还描述了用于实施所公开的方法的装置。

公开(公告)号：US06780695B1

公开(公告)日：2004-08-24

申请号：US10249563

申请日：2003-04-18

申请人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

发明人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

IPC分类号： H01L218238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

摘要翻译： 提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。 该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。 然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。 然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。 然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。

公开(公告)号：US06927476B2

公开(公告)日：2005-08-09

申请号：US09962738

申请日：2001-09-25

申请人： Gregory G. Freeman ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Kathryn T. Schonenberg ,  Shwu-Jen Jeng ,  Kenneth J. Stein ,  Jeffrey B. Johnson

发明人： Gregory G. Freeman ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Kathryn T. Schonenberg ,  Shwu-Jen Jeng ,  Kenneth J. Stein ,  Jeffrey B. Johnson

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/737 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing. The heterojunction bipolar transistor simultaneously improves three factors that affect the speed and performance of bipolar transistors: base width, base resistance, and base-collector capacitance.

摘要翻译： 本文公开了一种凸起的外在基极，硅锗（SiGe）异质结双极晶体管（HBT）及其制造方法。 异质结双极晶体管包括基板，形成在基板上的硅锗层，形成在基板上的集电极层，形成在硅锗层上的升高的非本征基极层和形成在硅锗层上的发射极层。 硅锗层在发射极层和凸起的非本征基极层之间形成异质结。 双极晶体管还包括形成在凸起的非本征基极层的一部分上的基极，在集电极层的一部分上形成的集电极，以及形成在发射极层的一部分上的发射极。 因此，异质结双极晶体管包括自对准凸起的外在基极，最小结深度以及影响基底宽度的最小间隙缺陷，全部以最小的热处理形成。 异质结双极晶体管同时改善了影响双极晶体管速度和性能的三个因素：基极宽度，基极电阻和基极集电极电容。

公开(公告)号：US06798029B2

公开(公告)日：2004-09-28

申请号：US10434999

申请日：2003-05-09

申请人： Richard P. Volant ,  John C. Bisson ,  Donna R. Cote ,  Timothy J. Dalton ,  Robert A. Groves ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Seshadri Subbanna

发明人： Richard P. Volant ,  John C. Bisson ,  Donna R. Cote ,  Timothy J. Dalton ,  Robert A. Groves ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Seshadri Subbanna

IPC分类号： H01L2982

CPC分类号： H01H59/0009 ,  H01H2059/0018 ,  H01H2059/0072

摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

摘要翻译： 描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。 该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。 该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。 铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。 在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。 气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。 代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。 下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。 通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。 然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。 然后用牺牲脱模材料填充空腔。 然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

公开(公告)号：US5731619A

公开(公告)日：1998-03-24

申请号：US651353

申请日：1996-05-22

申请人： Seshadri Subbanna

发明人： Seshadri Subbanna

IPC分类号： H01L21/8249 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L27/02 ,  H01L21/265

CPC分类号： H01L29/1079 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1075 ,  H01L29/7394

摘要： A CMOS integrated circuit with field isolation including an NFET(s) having an isolated P-well, wherein the isolated P-well is adjusted so that it does not extend below the field isolation (e.g., STI) and the width and doping of the P-well and an underlying buried N-well is adjusted so that the depletion regions of the source/drain (S-D) diode and also the well-diode just meet (merge) without overlap in the P-well. The semiconductor device obtains bipolar effect and reduced junction capacitance in a bulk single-crystal technology. A method for fabricating the semiconductor device if also provided.

摘要翻译： 具有场隔离的CMOS集成电路，其包括具有隔离P阱的NFET，其中调节分离的P阱，使得其不延伸到场隔离（例如，STI）以下的宽度和掺杂 调整P阱和下层掩埋的N阱，使得源极/漏极（SD）二极管的耗尽区以及阱二极管仅在P阱中满足（合并）而不重叠。 该半导体器件在大批量单晶技术中获得双极效应和降低的结电容。 如果还提供制造半导体器件的方法。

公开(公告)号：US5194397A

公开(公告)日：1993-03-16

申请号：US710498

申请日：1991-06-05

申请人： Robert K. Cook ,  Ronald W. Knepper ,  Subodh K. Kulkarni ,  Russell C. Lange ,  Paul A. Ronsheim ,  Seshadri Subbanna ,  Manu J. Tejwani ,  Bob H. Yun

发明人： Robert K. Cook ,  Ronald W. Knepper ,  Subodh K. Kulkarni ,  Russell C. Lange ,  Paul A. Ronsheim ,  Seshadri Subbanna ,  Manu J. Tejwani ,  Bob H. Yun

IPC分类号： H01L21/205 ,  H01L21/225 ,  H01L21/285 ,  H01L21/316 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/2256 ,  H01L21/28525 ,  H01L21/31662 ,  Y10S148/017 ,  Y10S148/124 ,  Y10S438/974

摘要： A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

公开(公告)号：US06933186B2

公开(公告)日：2005-08-23

申请号：US09961009

申请日：2001-09-21

申请人： John M. Cotte ,  Kenneth J. Stein ,  Seshadri Subbanna ,  Richard P. Volant

发明人： John M. Cotte ,  Kenneth J. Stein ,  Seshadri Subbanna ,  Richard P. Volant

IPC分类号： H01C17/26 ,  H01L21/02 ,  H01L21/337

CPC分类号： H01L28/24 ,  H01C17/262

摘要： A method of improving the tolerance of a back-end-of-the-line (BEOL) thin film resistor is provided. Specifically, the method of the present invention includes an anodization step which is capable of converting a portion of base resistor film into an anodized region. The anodized resistor thus formed has a sheet resistivity that is higher than that of the base resistor film.

摘要翻译： 提供了一种改进后端（BEOL）薄膜电阻的公差的方法。 具体地，本发明的方法包括能够将基极电阻膜的一部分转变为阳极氧化区域的阳极氧化步骤。 如此形成的阳极氧化电阻的电阻率比基极电阻膜高。

公开(公告)号：US06800503B2

公开(公告)日：2004-10-05

申请号：US10300520

申请日：2002-11-20

申请人： Joseph T. Kocis ,  James Tornello ,  Kevin S. Petrarca ,  Richard Volant ,  Seshadri Subbanna

发明人： Joseph T. Kocis ,  James Tornello ,  Kevin S. Petrarca ,  Richard Volant ,  Seshadri Subbanna

IPC分类号： H01L2100

CPC分类号： B81C1/00666 ,  B81B2201/014 ,  B81C2201/0167 ,  H01F2007/068 ,  H01H50/005

摘要： A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.

摘要翻译： 一种制造封装的微电子机械系统（MEMS）的方法及其制造方法，包括形成电介质层，图案化介电层的上表面以形成沟槽，在沟槽内形成释放材料，图案化上表面 形成另一个沟槽，形成第一封装层，该第一封装层包括另一个沟槽内的侧壁，在第一封装层内形成核心层，以及在芯层上方形成第二封装层，其中第二封装层被连接 到第一封装层的侧壁。 或者，该方法包括通过光掩模工艺形成多层MEMS结构以形成第一金属层，第二层包括电介质层和第二金属层以及第三金属层。 芯层和封装层由具有互补的电，机械和/或磁性的材料制成。

公开(公告)号：US06448124B1

公开(公告)日：2002-09-10

申请号：US09439067

申请日：1999-11-12

申请人： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

发明人： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

IPC分类号： H01L218238

CPC分类号： H01L21/76224 ,  H01L21/763 ,  H01L21/8249

摘要： A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

摘要翻译： 提供一种形成BiCMOS集成电路的方法，其包括以下步骤：（a）在衬底的第一区域中形成双极器件的第一部分; （b）在所述第一区域上形成第一保护层以保护所述双极器件的所述第一部分; （c）在所述衬底的第二区域中形成场效应晶体管器件; （d）在所述衬底的所述第二区域上形成第二保护层以保护所述场效应晶体管器件; （e）去除所述第一保护层; （f）在所述衬底的所述第一区域中形成所述双极器件的第二部分; 和（g）去除所述第二保护层。

公开(公告)号：US06414371B1

公开(公告)日：2002-07-02

申请号：US09580130

申请日：2000-05-30

申请人： Gregory G. Freeman ,  Robert A. Groves ,  Jeffrey Johnson ,  Seshadri Subbanna ,  Richard P. Volant

发明人： Gregory G. Freeman ,  Robert A. Groves ,  Jeffrey Johnson ,  Seshadri Subbanna ,  Richard P. Volant

IPC分类号： H01L27082

CPC分类号： H01L29/66242 ,  H01L21/8222 ,  H01L27/0823

摘要： High frequency performance of transistor designs is enhanced and manufacturing yield improved by removing and reducing sources of parasitic capacitance through combinations of processes from different technologies. After formation of collector, base and emitter regions on a substrate and attachment of a second substrate, the original substrate is wholly or partially removed, the inactive collector area is removed or rendered semi-insulating and wiring and contacts are made from the original back side of the chip. Dielectric material used in the manufacturing process can be removed to further reduce capacitance. The high frequency transistors can be bonded to CMOS chips or wafers to form BICMOS chips.

摘要翻译： 提高了晶体管设计的高频性能，并通过不同技术的工艺组合来去除和减少寄生电容源，从而提高了制造成品率。 在衬底上形成集电极，基极和发射极区域并附接第二衬底后，原始衬底被全部或部分去除，非活性集电极区域被去除或呈半绝缘，并且布线和接触由原始背面制成 的芯片。 可以去除在制造过程中使用的介电材料，以进一步降低电容。 高频晶体管可以结合到CMOS芯片或晶圆上以形成BICMOS芯片。