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公开(公告)号：US07585740B2
公开(公告)日：2009-09-08
申请号：US11308259
申请日：2006-03-14
IPC分类号： H01L21/331
CPC分类号： H01L29/1004 , H01L29/1608 , H01L29/66242 , H01L29/66287 , H01L29/732 , H01L29/7378
摘要： A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.
摘要翻译： 一种系统和方法包括在收集器上形成固有碱基。 该系统和方法还包括通过在预定温度下的自限硅化工艺在本征基底上形成完全硅化的外在碱，并且预定量的时间，硅化物在本征碱基本上停止。 该系统和方法还包括形成与外部基极和集电器物理绝缘的发射极，并与内部基极物理接触。
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2.发明申请HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH SELF-ALIGNED SUB-LITHOGRAPHIC METAL-SEMICONDUCTOR ALLOY BASE CONTACTS 有权具有自对准亚垂直金属 - 半导体合金基底接触的异相双极晶体管（HBT）公开(公告)号：US20080164495A1
公开(公告)日：2008-07-10
申请号：US11621864
申请日：2007-01-10
申请人： Guy M. Cohen , Francois Pagette
发明人： Guy M. Cohen , Francois Pagette
IPC分类号： H01L29/737 , H01L21/04
CPC分类号： H01L29/737 , H01L29/1004 , H01L29/66242
摘要： A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.
摘要翻译： 公开了一种异质结双极晶体管结构，其具有包括自对准金属半导体合金和自底向金属触点的自对准亚光刻非本征基极区域。 外部基极区域的横向尺寸由牺牲间隔物的覆盖层限定，并且其厚度通过选择性外延进行控制。 使用与常规硅处理兼容的方法，将非对准半导体 - 金属合金和自对准金属接触制成外部基极。
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3.发明授权Heterojunction bipolar transistor (HBT) with self-aligned sub-lithographic metal-semiconductor alloy base contacts 有权具有自对准亚光刻金属 - 半导体合金基底触点的异质结双极晶体管（HBT）公开(公告)号：US07952165B2
公开(公告)日：2011-05-31
申请号：US11621864
申请日：2007-01-10
申请人： Guy M. Cohen , Francois Pagette
发明人： Guy M. Cohen , Francois Pagette
IPC分类号： H01L27/082
CPC分类号： H01L29/737 , H01L29/1004 , H01L29/66242
摘要： A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.
摘要翻译： 公开了一种异质结双极晶体管结构，其具有包括自对准金属半导体合金和自底向金属触点的自对准亚光刻非本征基区。 外部基极区域的横向尺寸由牺牲间隔物的覆盖层限定，并且其厚度通过选择性外延进行控制。 使用与常规硅处理兼容的方法，将非对准半导体 - 金属合金和自对准金属接触制成外部基极。
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公开(公告)号：US06448131B1
公开(公告)日：2002-09-10
申请号：US09929182
申请日：2001-08-14
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , H01L29/66181 , Y10S438/964
摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.
摘要翻译： 提供了一种用于增加沟槽电容器表面积的方法。 利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。 可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。 一旦金属沉积在沟槽中，该方法是自限制的。 通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。
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5.发明授权Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices 有权用于减少浅结和薄SOI电子器件中Si消耗的自对准硅化物工艺公开(公告)号：US06444578B1
公开(公告)日：2002-09-03
申请号：US09791024
申请日：2001-02-21
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
摘要翻译： 本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。 本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。
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公开(公告)号：US09728619B2
公开(公告)日：2017-08-08
申请号：US13610266
申请日：2012-09-11
IPC分类号： H01L29/423 , B82Y10/00 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/66439 , H01L29/78696
摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.
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公开(公告)号：US08921825B2
公开(公告)日：2014-12-30
申请号：US13608089
申请日：2012-09-10
IPC分类号： H01L29/06 , H01L29/786 , H01L29/423 , B82Y10/00 , H01L29/66 , H01L29/775
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , Y10S977/938
摘要： A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.
摘要翻译： 场效应晶体管器件包括纳米线，包括设置在纳米线上的栅极电介质层的栅极堆叠，设置在电介质层上的栅极导体层和衬底，以及包括设置在基板上的侧壁接触部分的有源区域， 栅极堆叠，侧壁接触部分与纳米线电接触。
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公开(公告)号：US08680510B2
公开(公告)日：2014-03-25
申请号：US12824288
申请日：2010-06-28
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0243 , H01L21/02521 , H01L21/02543 , H01L21/02603 , H01L21/02658 , H01L29/0673 , H01L29/068 , H01L29/125 , H01L29/42392 , H01L29/775 , H01L29/778 , H01L29/78681 , H01L29/78696
摘要： A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects.
摘要翻译： 提供了形成半导体的方法，并且包括将衬垫和纳米线图案化到晶片上，所述纳米线基本上与衬垫侧壁垂直并且基本上平行于晶片表面并且外延生长在纳米线的外表面上， 半导体材料，其相对于纳米线的材料而晶格失配并且基本上没有缺陷。
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公开(公告)号：US20140014904A1
公开(公告)日：2014-01-16
申请号：US13558532
申请日：2012-07-26
申请人： Guy M. Cohen , Michael A. Guillorn
发明人： Guy M. Cohen , Michael A. Guillorn
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/413 , H01L29/42364 , H01L29/66439
摘要： In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.
摘要翻译： 一方面，提供一种FET器件。 FET器件包括衬底; 衬底上的半导体材料; 所述衬底上的至少一个栅极围绕用作所述器件的沟道区的所述半导体材料的一部分，其中从所述栅极延伸的所述半导体材料的部分用作所述器件的源极和漏极区域，并且其中所述源极和 器件的漏极区域从衬底移位; 覆盖栅极和半导体材料的器件上的平坦化电介质; 以及延伸穿过平坦化电介质并且围绕器件的源极和漏极区域的触点。
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10.发明授权CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins 失效具有沟道P-FinFET和沟道N-FinFET的CMOS具有不同的晶体取向和平行鳍片公开(公告)号：US08574969B2
公开(公告)日：2013-11-05
申请号：US13560322
申请日：2012-07-27
申请人： Guy M. Cohen , Katherine L. Saenger
发明人： Guy M. Cohen , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L27/0924 , H01L21/34 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit fabrication apparatus is configured to fabricate an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. A bonding control processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A material growth processor is configured to form a volume of material extending through the first silicon layer from the second layer up to the surface of first layer. The material has a crystalline orientation that substantially matches the crystalline orientation of second layer. An etching processor is configured to selectively etch areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins.
摘要翻译： 集成电路制造装置被配置为制造具有至少一个p-FinFET器件和至少一个n-FinFET器件的集成电路。 键合控制处理器被配置为将具有第一晶体取向的第一硅层与具有不同于第一晶体取向的第二晶体取向的第二硅层结合。 材料生长处理器被配置为形成从第二层延伸穿过第一硅层到第一层的表面的材料体积。 该材料具有基本上与第二层的晶体取向一致的结晶取向。 蚀刻处理器被配置为选择性地蚀刻位于该区域外部的第一层的表面的区域，以在该区域内形成第一多个散热片和区域，以产生第二多个翅片。
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