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    Novel structure for a multiple-gate FET device and a method for its fabrication
    4.
    发明申请
    Novel structure for a multiple-gate FET device and a method for its fabrication 有权
    用于多栅极FET器件的新型结构及其制造方法

    公开(公告)号：US20070026629A1

    公开(公告)日：2007-02-01

    申请号：US11192494

    申请日：2005-07-29

    申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu

    发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu

    IPC分类号： H01L21/76 ,  H01L21/302

    CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7851

    摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

    摘要翻译： 提供了一种用于形成半导体器件的方法和使用该方法制造的器件。 在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。 通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。 沟槽部分地填充有电介质材料。 去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

    Semiconductor device employing an extension spacer and a method of forming the same
    5.
    发明申请
    Semiconductor device employing an extension spacer and a method of forming the same 有权
    采用延伸间隔物的半导体装置及其形成方法

    公开(公告)号：US20060102955A1

    公开(公告)日：2006-05-18

    申请号：US10989073

    申请日：2004-11-15

    申请人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

    发明人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

    IPC分类号： H01L21/338 ,  H01L31/062

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76829 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7843

    摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.

    摘要翻译： 形成在半导体衬底上的半导体器件及其形成方法。 在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。 该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。 半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。 源极/漏极延伸在电介质衬垫和延伸垫片下面。 半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。 因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

    Semiconductor device employing an extension spacer and a method of forming the same
    6.
    发明授权
    Semiconductor device employing an extension spacer and a method of forming the same 有权
    采用延伸间隔物的半导体装置及其形成方法

    公开(公告)号：US07265425B2

    公开(公告)日：2007-09-04

    申请号：US10989073

    申请日：2004-11-15

    申请人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

    发明人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76829 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7843

    摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.

    摘要翻译： 形成在半导体衬底上的半导体器件及其形成方法。 在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。 该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。 半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。 源极/漏极延伸在电介质衬垫和延伸垫片下面。 半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。 因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

    FIN FILLED EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME
    8.
    发明申请
    FIN FILLED EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME 有权
    FIN填充效应晶体管及其形成方法

    公开(公告)号：US20080277745A1

    公开(公告)日：2008-11-13

    申请号：US11744896

    申请日：2007-05-07

    申请人： Ju-Wang Hsu ,  Chih-Yuan Ting ,  Tang-Xuan Zhong ,  Yi-Nien Su ,  Jang-Shiang Tsai

    发明人： Ju-Wang Hsu ,  Chih-Yuan Ting ,  Tang-Xuan Zhong ,  Yi-Nien Su ,  Jang-Shiang Tsai

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/7851 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

    摘要： A fin field effect transistor and method of forming the same. The fin field effect transistor comprises a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further comprises shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further comprises a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

    摘要翻译： 翅片场效应晶体管及其形成方法。 鳍状场效应晶体管包括具有翅片结构的半导体衬底和具有顶部和底部的两个沟槽之间。 鳍状场效应晶体管还包括在沟槽的底部形成的浅沟槽隔离物和鳍状结构上的栅电极和浅沟槽隔离，其中栅电极基本上垂直于鳍结构。 翅片场效应晶体管还包括沿翅片结构的侧壁和形成在鳍结构中的源/漏电极的栅介质层。

    Fin field effect transistor and method of forming the same
    9.
    发明授权
    Fin field effect transistor and method of forming the same 有权
    Fin场效应晶体管及其形成方法

    公开(公告)号：US08927353B2

    公开(公告)日：2015-01-06

    申请号：US11744896

    申请日：2007-05-07

    申请人： Ju-Wang Hsu ,  Chih-Yuan Ting ,  Tang-Xuan Zhong ,  Yi-Nien Su ,  Jang-Shiang Tsai

    发明人： Ju-Wang Hsu ,  Chih-Yuan Ting ,  Tang-Xuan Zhong ,  Yi-Nien Su ,  Jang-Shiang Tsai

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/7851 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

    摘要： A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

    摘要翻译： 翅片场效应晶体管及其形成方法。 翅片场效应晶体管包括具有翅片结构的半导体衬底和具有顶部和底部的两个沟槽之间。 鳍状场效应晶体管还包括在沟槽的底部形成的浅沟槽隔离物和鳍状结构上的栅电极和浅沟槽隔离，其中栅电极基本上垂直于鳍结构。 翅片场效应晶体管还包括沿翅片结构的侧壁和形成在鳍结构中的源/漏电极的栅介质层。