公开(公告)号：US3726002A

公开(公告)日：1973-04-10

申请号：US3726002D

申请日：1971-08-27

Applicant: IBM

Inventor： GREENSTEIN B ,  TURETZKY M ,  LANGSTON P ,  NARKEN B

IPC: H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H05K1/03 ,  H05K3/10 ,  H05K3/20 ,  H05K3/24 ,  H05K3/46 ,  B01J17/00

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/5383 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/108 ,  H05K3/205 ,  H05K3/243 ,  H05K3/4647 ,  H05K3/4664 ,  H05K3/4667 ,  H05K3/467 ,  H05K2201/09509 ,  H05K2203/0733 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/4916 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A process for fabricating a high performance electrical interconnection package for a plurality of semiconductor chips including the steps of selecting an appropriate dissimilar refractory substrate, forming a plurality of bubble-free layers of glass over the substrate, depositing a plurality of planar metallization patterns on each layer of deposited glass, selectively depositing vertical studs for electrical interconnection between various conductive patterns, and bonding a plurality of integrated circuit chips to the upper surface of the glass package.

Abstract translation: 一种用于制造用于多个半导体芯片的高性能电互连封装件的方法，包括以下步骤：选择合适的不同耐火基材，在基板上形成多个无气泡玻璃层，在每个半导体芯片上沉积多个平面金属化图案 沉积玻璃层，选择性地沉积用于各种导电图案之间的电互连的垂直螺柱，以及将多个集成电路芯片接合到玻璃封装的上表面。