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    CIRCUIT BOARD HAVING VIA AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    CIRCUIT BOARD HAVING VIA AND MANUFACTURING METHOD THEREOF 有权
    具有通风功能的电路板及其制造方法

    公开(公告)号：US20150181693A1

    公开(公告)日：2015-06-25

    申请号：US14226526

    申请日：2014-03-26

    Applicant: Industrial Technology Research Institute

    Inventor： Shih-Hsien WU ,  Min-Lin LEE

    IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11

    CPC classification number: H05K1/0227 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4685 ,  H05K2201/09854 ,  Y10T29/49165

    Abstract: The disclosure provides a manufacturing method for a circuit board having a via and including a substrate, a ground conductor, a floated conductor and a signal conductor. The substrate includes a second sheet layer, a second ground layer, a core layer, a first ground layer and a first sheet layer that are stacked in sequence from bottom to top. The ground conductor penetrates through the core layer and is electrically coupled to the first ground layer and the second ground layer. The floated conductor penetrates through the core layer and is electrically insulated from the first ground layer, the second ground layer and the ground conductor. The signal conductor penetrates through the substrate, being located between the ground conductor and the floated conductor, and insulated from the first ground layer, the second ground layer, the ground conductor and the floated conductor.

    Abstract translation: 本发明提供了一种具有通孔并且包括衬底，接地导体，浮动导体和信号导体的电路板的制造方法。 基板包括从底部到顶部依次层叠的第二片层，第二接地层，芯层，第一接地层和第一片层。 接地导体穿过芯层并电耦合到第一接地层和第二接地层。 浮动导体穿过芯层，并与第一接地层，第二接地层和接地导体电绝缘。 信号导体穿过衬底，位于接地导体和浮动导体之间，并与第一接地层，第二接地层，接地导体和浮动导体绝缘。

    SEMICONDUCTOR SUBSTRATE ASSEMBLY
    2.
    发明申请
    SEMICONDUCTOR SUBSTRATE ASSEMBLY 有权
    半导体基板组件

    公开(公告)号：US20150097298A1

    公开(公告)日：2015-04-09

    申请号：US14570684

    申请日：2014-12-15

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Peng-Shu CHEN ,  Shih-Hsien WU

    IPC: H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/481 ,  H01L21/02107 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/64 ,  H01L23/66 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/81192 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3011

    Abstract: A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a second conductive pillar. The semiconductor material layer has a first surface and a second surface opposite to the first surface. The first isolation layer is located on the first surface of the semiconductor material layer. The second isolation layer is located on the second surface of the semiconductor material layer. The first conductive pillar, supplied with a first voltage, penetrates the semiconductor material layer, the first isolation layer, and the second isolation layer. The second conductive pillar is supplied with to a second voltage, and a part of the second conductive pillar is formed in the second isolation layer, the second conductive pillar penetrates the second isolation layer and touches the second surface of the semiconductor material layer.

    Abstract translation: 半导体衬底组件包括半导体材料层，第一隔离层，第二隔离层，第一导电柱和第二导电柱。 半导体材料层具有与第一表面相对的第一表面和第二表面。 第一隔离层位于半导体材料层的第一表面上。 第二隔离层位于半导体材料层的第二表面上。 提供有第一电压的第一导电柱穿透半导体材料层，第一隔离层和第二隔离层。 第二导电柱被提供到第二电压，并且第二导电柱的一部分形成在第二隔离层中，第二导电柱穿透第二隔离层并接触半导体材料层的第二表面。

    ELECTRONIC DEVICE HAVING SUBSTRATE
    3.
    发明公开
    ELECTRONIC DEVICE HAVING SUBSTRATE 审中-公开

    公开(公告)号：US20230187332A1

    公开(公告)日：2023-06-15

    申请号：US17550602

    申请日：2021-12-14

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Tsung-Yi HUNG ,  Shih-Hsien WU

    IPC: H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L24/16 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16227

    Abstract: An electronic device includes a substrate, an upper conductive layer, and a lower conductive layer. The substrate has a plurality of inner vias and has an upper surface and a lower surface. The upper conductive layer includes an upper ground trace and an upper signal pad disposed on the upper surface. The upper ground trace is electrically connected to the ground vias and has an upper hollow portion exposing a part of the upper surface. The upper signal pad is disposed on the part of the upper surface exposed by the upper hollow portion and electrically connected to the signal via. The lower conductive layer includes a lower ground trace and a lower signal pad disposed on the lower surface. The lower conductive trace is electrically connected to the ground vias and has a lower hollow portion exposing a part of the lower surface. The lower signal pad is disposed on the part of the lower surface exposed by the lower hollow portion and electrically connected to the signal via.

    CIRCUIT STRUCTURE
    4.
    发明申请
    CIRCUIT STRUCTURE 有权

    公开(公告)号：US20210203052A1

    公开(公告)日：2021-07-01

    申请号：US16821283

    申请日：2020-03-17

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Hsiang En DING ,  Shih-Hsien WU

    IPC: H01P3/08 ,  H01P11/00

    Abstract: A circuit structure includes a substrate integrated waveguide, a substrate disposed on the substrate integrated waveguide, a waveguide signal feeding element and a ring-shaped conductive element. The substrate integrated waveguide includes another substrate having a waveguide transmitting region, two conductive layers disposed on this substrate and covering the waveguide transmitting region, and at least one waveguide conductive element passing through this substrate and electrically connected to the two conductive layers. The at least one waveguide conductive element surrounds the waveguide transmitting region. One of the conductive layers is located between the two substrates. The waveguide signal feeding element passes through one substrate and one conductive layer between the substrates, and the waveguide signal feeding element extends to the waveguide transmitting region. The waveguide signal feeding element is electrically insulated from one conductive layer. The ring-shaped conductive element is disposed in one substrate and surrounds the waveguide signal feeding element.

    CIRCUIT STRUCTURE
    6.
    发明申请
    CIRCUIT STRUCTURE 审中-公开
    电路结构

    公开(公告)号：US20170019994A1

    公开(公告)日：2017-01-19

    申请号：US14968021

    申请日：2015-12-14

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Shih-Hsien WU

    IPC: H05K1/11 ,  H05K1/02

    CPC classification number: H05K1/0251 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09809

    Abstract: A circuit structure includes an annular conductor, a conductive via and at least one extension conductor. The annular conductor extends along a direction. The conductive via is disposed in the annular conductor and extending along the direction. The at least one extension conductor is electrically connected to at least one end of the annular conductor and extending toward the conductive via.

    Abstract translation: 电路结构包括环形导体，导电通孔和至少一个延伸导体。 环形导体沿着一个方向延伸。 导电通孔设置在环形导体中并沿着该方向延伸。 所述至少一个延伸导体电连接到所述环形导体的至少一个端部并朝向所述导电通孔延伸。

    ELECTRONIC DEVICE HAVING SUBSTRATE
    7.
    发明公开
    ELECTRONIC DEVICE HAVING SUBSTRATE 审中-公开

    公开(公告)号：US20230187361A1

    公开(公告)日：2023-06-15

    申请号：US17550474

    申请日：2021-12-14

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Tsung-Yi HUNG ,  Shih-Hsien WU

    IPC: H01L23/538 ,  H01L25/10

    CPC classification number: H01L23/5382 ,  H01L25/105 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2225/1041 ,  H01L2225/1058

    Abstract: An electronic device includes a substrate, an outer layer, a conductive line layer, and a switchable circuit chip. The substrate has a plurality of having a plurality of first vias. The outer layer is disposed on a side of the substrate and has a plurality of second vias. The first vias have a larger distribution density or quantity than the second vias, so that a part of the first vias are electrically connected to the second vias, and another part of the first vias are electrically floating. The conductive line layer is disposed on the outer layer and has a plurality of conductive traces. The conductive traces are electrically connected to the second vias. The switchable circuit chip is electrically connected to the first vias. The conductive traces are electrically connected to the switchable circuit chip. The switchable circuit chip is configured for controlling an electrical connecting relationship between the conductive traces and the first vias and an electrical connecting relationship among the conductive traces.

    LEAD FRAME PACKAGE
    10.
    发明申请
    LEAD FRAME PACKAGE 有权

    公开(公告)号：US20220005754A1

    公开(公告)日：2022-01-06

    申请号：US17031486

    申请日：2020-09-24

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Ren-Shin CHENG ,  Shih-Hsien WU ,  Yu-Wei HUANG ,  Chih Ming SHEN ,  Yi-Chieh TSAI

    IPC: H01L23/495 ,  H01L23/498

    Abstract: A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.

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