公开(公告)号：US20140087549A1

公开(公告)日：2014-03-27

申请号：US13710795

申请日：2012-12-11

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Wen-Ching SUN ,  Sheng-Min YU ,  Tai-Jui WANG ,  Tzer-Shen LIN

IPC: H01L21/22

CPC classification number: H01L21/225 ,  H01L21/22 ,  H01L21/2255 ,  H01L31/068 ,  H01L31/18 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate.

Abstract translation: 公开了一种用于形成掺杂区域的方法，包括提供衬底，在衬底上形成第一类掺杂材料，并在衬底上形成第二类掺杂材料，其中第一类型掺杂材料与第二类掺杂材料分离 掺杂材料缺口; 形成覆盖所述基板的覆盖层，所述第一类型掺杂材料和所述第二类型掺杂材料; 并且进行热扩散处理以将第一种掺杂材料和第二类型掺杂材料扩散到衬底中。

公开(公告)号：US20140080313A1

公开(公告)日：2014-03-20

申请号：US13725419

申请日：2012-12-21

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sheng-Min YU ,  Wen-Ching SUN ,  Tai-Jui WANG ,  Yi-Fan CHEN ,  Chia-Liang SUN ,  Hao-Hsiang CHIANG ,  Pin-Guan LIAO ,  Chi-Fan CHIANG ,  Tzer-Shen LIN

IPC: H01L21/306

CPC classification number: H01L21/30604 ,  H01L31/02363 ,  Y02E10/50

Abstract: An etching composition for a semiconductor wafer is provided, including 0.5-50 wt % base, 10-80 wt % alcohol, 0.01-15 wt % additive and water. A method for etching a semiconductor wafer is also provided. When the etching composition is applied to the entire surface or a partial surface of the semiconductor wafer at 60-200° C., the etching composition reacts on the semiconductor wafer to form a foam that etches the semiconductor wafer and includes a solid, a liquid and a gas. At the same time, the additive forms an oxide mask on the surface of the semiconductor wafer. Therefore, an excellent texture structure is formed on the surface of the semiconductor wafer, and a single surface of the semiconductor wafer is etched.

Abstract translation: 提供了一种用于半导体晶片的蚀刻组合物，其包括0.5-50重量％的碱，10-80重量％的醇，0.01-15重量％的添加剂和水。 还提供了蚀刻半导体晶片的方法。 当在60-200℃下将蚀刻组合物施加到半导体晶片的整个表面或部分表面时，蚀刻组合物在半导体晶片上反应形成蚀刻半导体晶片的泡沫，并且包括固体，液体 和气体。 同时，添加剂在半导体晶片的表面形成氧化物掩模。 因此，在半导体晶片的表面上形成优良的纹理结构，并且蚀刻半导体晶片的单个表面。

公开(公告)号：US20150162196A1

公开(公告)日：2015-06-11

申请号：US14626675

申请日：2015-02-19

Applicant: Industrial Technology Research Institute

Inventor： Wen-Ching SUN ,  Sheng-Min YU ,  Tai-Jui WANG ,  Tzer-Shen LIN

IPC: H01L21/225 ,  H01L31/18

CPC classification number: H01L21/225 ,  H01L21/22 ,  H01L21/2255 ,  H01L31/068 ,  H01L31/18 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate.

Abstract translation: 公开了一种用于形成掺杂区域的方法，包括提供衬底，在衬底上形成第一类掺杂材料，并在衬底上形成第二类掺杂材料，其中第一类型掺杂材料与第二类掺杂材料分离 掺杂材料缺口; 形成覆盖所述基板的覆盖层，所述第一类型掺杂材料和所述第二类型掺杂材料; 并且进行热扩散处理以将第一种掺杂材料和第二类型掺杂材料扩散到衬底中。

公开(公告)号：US20140042440A1

公开(公告)日：2014-02-13

申请号：US14058403

申请日：2013-10-21

Applicant: Industrial Technology Research Institute

Inventor： Wen-Ching SUN ,  Tzer-Shen LIN ,  Sheng-Min YU

IPC: H01L31/0216 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L31/02167 ,  C23C18/1216 ,  C23C18/1245 ,  C23C18/1258 ,  C23C18/1287 ,  C23C18/1291 ,  H01L21/02178 ,  H01L21/02282 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/66462 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/1868 ,  H01L33/44 ,  Y02E10/547 ,  Y02P70/521

Abstract: A passivation layer structure of a semiconductor device is provided, which includes a passivation layer formed of halogen-doped aluminum oxide and disposed on a semiconductor layer on a substrate, in which the semiconductor layer includes indium gallium zinc oxide (IGZO) or nitride-based III-V compounds. A method for forming the passivation layer structure of a semiconductor device is also disclosed.

Abstract translation: 提供半导体器件的钝化层结构，其包括由卤素掺杂的氧化铝形成的钝化层，并且设置在衬底上的半导体层上，其中半导体层包括铟镓锌氧化物（IGZO）或氮化物基 III-V族化合物。 还公开了一种用于形成半导体器件的钝化层结构的方法。