公开(公告)号：US20150039805A1

公开(公告)日：2015-02-05

申请号：US13957604

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Ulrich Backhausen ,  Thomas Kern ,  Thomas Nirschl ,  Jens Rosenbusch ,  Xiangting Bi ,  Edvin Paparisto

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1032 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C2029/1806

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于模拟电可擦除可编程只读存储器的系统，以及用于模拟电可擦除可编程只读存储器的方法。 根据本公开的实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，所述系统包括第一存储器部分和第二存储器部分，其中第一存储器部分包括多个存储位置，其被配置为存储 数据被分割成多个数据段，并且其中第二存储器部分被配置为存储将存储在第一存储器部分中的数据段的物理地址映射到数据段的逻辑地址的信息。

公开(公告)号：US20140215124A1

公开(公告)日：2014-07-31

申请号：US13751883

申请日：2013-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Wolf Allers ,  Jan Otterstedt ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3486

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

Abstract translation: 本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。 根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择 用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。

公开(公告)号：US09569354B2

公开(公告)日：2017-02-14

申请号：US13957604

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Ulrich Backhausen ,  Thomas Kern ,  Thomas Nirschl ,  Jens Rosenbusch ,  Xiangting Bi ,  Edvin Paparisto

IPC: G06F12/02 ,  G06F11/10 ,  G11C29/18

CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1032 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C2029/1806

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于模拟电可擦除可编程只读存储器的系统，以及用于模拟电可擦除可编程只读存储器的方法。 根据本公开的实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，所述系统包括第一存储器部分和第二存储器部分，其中第一存储器部分包括多个存储位置，其被配置为存储 数据被分割成多个数据段，并且其中第二存储器部分被配置为存储将存储在第一存储器部分中的数据段的物理地址映射到数据段的逻辑地址的信息。

公开(公告)号：US09032140B2

公开(公告)日：2015-05-12

申请号：US13751883

申请日：2013-01-28

Applicant: Infineon Technologies AG

Inventor： Wolf Allers ,  Jan Otterstedt ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro

IPC: G11C16/10 ,  G06F12/02 ,  G11C16/06 ,  G11C16/24 ,  G11C16/34

CPC classification number: G06F12/0246 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3486

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

Abstract translation: 本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。 根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择 用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。