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    Reuse of electrical charge at a semiconductor memory device
    1.
    发明授权
    Reuse of electrical charge at a semiconductor memory device 有权

    公开(公告)号：US09659657B2

    公开(公告)日：2017-05-23

    申请号：US14955628

    申请日：2015-12-01

    Applicant: Infineon Technologies AG

    Inventor： Leonardo Castro ,  Giacomo Curatolo

    IPC: G11C16/08 ,  G11C8/08

    CPC classification number: G11C16/08 ,  G11C8/08

    Abstract: A semiconductor memory device having a plurality of decoders, wherein each decoder is assigned to a select line, wherein no other decoder is assigned to the select line, each decoder has an output configured to charge the select line to when the decoder is activated and to discharge the select line when said decoder is deactivated. Also, each decoder is configured such that, in case that a first decoder gets deactivated after being activated and a second decoder of the decoders gets activated after being deactivated, the output of the first decoder and the output of the second decoder get connected to a common node for a predefined time interval, so that an electrical charge may be transferred from the select line, to the first decoder is assigned to, to the select line, to which the second decoder is assigned to, before the output of the first decoder gets connected to a reference voltage and the output of the second decoder gets connected to a supply voltage.

    SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE
    3.
    发明申请
    SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE 有权
    用于存储器件的自适应位速率编程的系统和方法

    公开(公告)号：US20140215124A1

    公开(公告)日：2014-07-31

    申请号：US13751883

    申请日：2013-01-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Wolf Allers ,  Jan Otterstedt ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3486

    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

    Abstract translation: 本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。 根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择 用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。

    Circuit for injecting compensating charge in a bias line
    4.
    发明授权
    Circuit for injecting compensating charge in a bias line 有权

    公开(公告)号：US09892765B2

    公开(公告)日：2018-02-13

    申请号：US15095189

    申请日：2016-04-11

    Applicant: Infineon Technologies AG

    Inventor： Giacomo Curatolo ,  Leonardo Castro

    IPC: G11C7/06 ,  G05F3/26 ,  G11C7/02

    CPC classification number: G11C7/062 ,  G05F3/262 ,  G11C7/02 ,  G11C7/067 ,  G11C2207/063

    Abstract: According to one embodiment, a circuit is described including a circuit component configured to switch from a first state into a second state including a node whose potential changes by a predetermined voltage when the circuit component switches from the first state into the second state, a line coupled with the node wherein the switching of the circuit component from the first state into the second state draws or injects a predetermined charge from or into the line, a capacitor coupled to the line and a compensation circuit configured to generate a predetermined multiple of the predetermined voltage and to compensate the charge drawn from or injected into the line by driving the capacitor with the multiple of the predetermined voltage.

    System and method for adaptive bit rate programming of a memory device
    5.
    发明授权
    System and method for adaptive bit rate programming of a memory device 有权
    用于存储器件的自适应比特率编程的系统和方法

    公开(公告)号：US09032140B2

    公开(公告)日：2015-05-12

    申请号：US13751883

    申请日：2013-01-28

    Applicant: Infineon Technologies AG

    Inventor： Wolf Allers ,  Jan Otterstedt ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro

    IPC: G11C16/10 ,  G06F12/02 ,  G11C16/06 ,  G11C16/24 ,  G11C16/34

    CPC classification number: G06F12/0246 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3486

    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

    Abstract translation: 本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。 根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择 用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。

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