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    Devices, systems, and methods for implementing a real time clock
    1.
    发明授权
    Devices, systems, and methods for implementing a real time clock 有权

    公开(公告)号：US12072728B2

    公开(公告)日：2024-08-27

    申请号：US17975661

    申请日：2022-10-28

    Applicant: Infineon Technologies AG

    Inventor： Wei Wang ,  Lingyun Li ,  Mihail Jefremow ,  Holger Dienst ,  Juergen Schaefer ,  Soenke Ohls

    IPC: G06F1/12 ,  G06F1/08

    CPC classification number: G06F1/08 ,  G06F1/12

    Abstract: A device including at least one processor, and an analog-to-digital (ADC) circuit, wherein the at least one processor is configured to generate an excitation signal and provide the excitation signal to a crystal in a pierce oscillation configuration, wherein after providing the excitation signal, the ADC circuit is configured to obtain as input a signal output from the crystal and convert the signal to a digital output; the at least one processor is configured to compare the digital output of the ADC circuit to a plurality of thresholds and based on the comparisons is further configured to drive the crystal to cause the crystal to operate as a pierce oscillator and to generate a clock signal from at least of one of the comparisons.

    Symmetrical Differential Sensing Method and System for STT MRAM
    2.
    发明申请
    Symmetrical Differential Sensing Method and System for STT MRAM 审中-公开
    STT MRAM对称差分传感方法及系统

    公开(公告)号：US20150255136A1

    公开(公告)日：2015-09-10

    申请号：US14714796

    申请日：2015-05-18

    Applicant: Infineon Technologies AG

    Inventor： David Mueller ,  Wolf Allers ,  Mihail Jefremow

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1659 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

    Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.

    Abstract translation: 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 在一个示例中，用于读取存储器单元的系统包括感测路径和反向路径。 通过感测路径提供参考电流，并且通过感测路径中的第一采样元件进行采样，并且通过反向感测路径提供来自存储器单元的单元电流，并且经由反向感测路径中的第二采样元件进行采样 。 随后，存储器单元与反向感测路径断开，通过感测路径提供单元电流，参考源与感测路径断开，并通过反向感测路径提供参考电流。 然后，输出电平由电池和参考电流根据采样的参考和采样单元电流工作来确定。

    Non-linear inter-ADC calibration by time equidistant triggering
    5.
    发明授权
    Non-linear inter-ADC calibration by time equidistant triggering 有权

    公开(公告)号：US11621717B1

    公开(公告)日：2023-04-04

    申请号：US17519759

    申请日：2021-11-05

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Ralph Mueller-Eschenbach ,  Juergen Schaefer ,  Arndt Voigtlaender ,  David Zipperstein

    IPC: H03M1/10 ,  H03M1/50 ,  H03M1/46 ,  H03M1/12

    Abstract: A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.

    SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE
    6.
    发明申请
    SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE 有权
    用于存储器件的自适应位速率编程的系统和方法

    公开(公告)号：US20140215124A1

    公开(公告)日：2014-07-31

    申请号：US13751883

    申请日：2013-01-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Wolf Allers ,  Jan Otterstedt ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3486

    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

    Abstract translation: 本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。 根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择 用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。

    ELECTRONIC DEVICE
    7.
    发明申请
    ELECTRONIC DEVICE 有权

    公开(公告)号：US20220399886A1

    公开(公告)日：2022-12-15

    申请号：US17836181

    申请日：2022-06-09

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  David Zipperstein ,  Juergen Schaefer ,  Holger Dienst ,  Markus Bichl ,  Ralph Mueller-Eschenbach ,  Arndt Voigtlaender

    IPC: H03K17/56 ,  H03M3/00

    Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

    SENSE AMPLIFIER OF A MEMORY CELL
    9.
    发明申请
    SENSE AMPLIFIER OF A MEMORY CELL 有权
    记忆体的感应放大器

    公开(公告)号：US20150194192A1

    公开(公告)日：2015-07-09

    申请号：US14149353

    申请日：2014-01-07

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Mihail Jefremow

    IPC: G11C7/06 ,  G11C7/12

    CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C16/26

    Abstract: A sense amplifier of a memory cell having a sense voltage generating circuit configured to generate a sense voltage; and a sensing circuit configured to compare a bitline voltage of the memory cell with the sense voltage, and to output a digital output signal indicating a content of the memory cell, wherein during a sense phase, the sensing circuit is decoupled from a voltage supply which charges a bitline capacitance during a precharge phase, and is coupled to and supplied by the bitline capacitance. The sense voltage generating circuit may be further configured to generate a sense voltage that during a precharge phase is dependent on the voltage supply and during a sense phase is independent of the voltage supply.

    Abstract translation: 具有感测电压发生电路的存储单元的读出放大器被配置为产生检测电压; 以及感测电路，被配置为将存储器单元的位线电压与感测电压进行比较，并且输出指示存储器单元的内容的数字输出信号，其中在感测阶段期间，感测电路与电压源 在预充电阶段期间对位线电容充电，并且被位线电容耦合并由位线电容提供。 感测电压产生电路还可以被配置为产生在预充电阶段期间取决于电压供应并且在感测阶段期间独立于电压供应的感测电压。

    Resolver-to-digital conversion with rotation speed offset
    10.
    发明授权
    Resolver-to-digital conversion with rotation speed offset 有权

    公开(公告)号：US12206344B2

    公开(公告)日：2025-01-21

    申请号：US18069307

    申请日：2022-12-21

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Jürgen Schäfer ,  Michael Augustin ,  Chandresh Patel ,  Arndt Voigtländer

    IPC: H03M1/48 ,  H02P21/09 ,  H02P21/10

    Abstract: A resolver-to-digital converter, comprising: a feedback (FB) filter chain loop having a state observer configured to estimate a rotation speed and a rotation angle of an object, based on a pair of input sine and cosine signals that are amplitude-modulated (AM) to correspond with the rotation angle of the object; and a feedforward (FF) filter chain path configured to estimate the rotation speed of the object based on the pair of input sine and cosine signals, wherein the state observer of the FB filter chain loop is further configured to offset the estimated rotation speed of the FB filter chain loop with the estimated rotation speed of the FF filter chain path to decrease a settling time of the estimated rotation angle.

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