公开(公告)号：US20210312979A1

公开(公告)日：2021-10-07

申请号：US17218373

申请日：2021-03-31

Applicant: Infineon Technologies AG

Inventor： Wolf Allers ,  Jan Otterstedt ,  Christian Peters

IPC: G11C13/00 ,  G11C11/16

Abstract: Read circuitry for a memory cell of a resistive change memory is suggested, wherein a signal of a bit-line that is connected to the memory cell is compared with a reference signal, and wherein the reference signal is determined based on a first dummy circuit that determines a leakage current of memory cells addressed by the bit-line. Also, a corresponding method is provided.

公开(公告)号：US20140215124A1

公开(公告)日：2014-07-31

申请号：US13751883

申请日：2013-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Wolf Allers ,  Jan Otterstedt ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3486

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

Abstract translation: 本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。 根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择 用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。

公开(公告)号：US11562789B2

公开(公告)日：2023-01-24

申请号：US17117713

申请日：2020-12-10

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Wolf Allers ,  Christian Peters

IPC: G11C17/16 ,  G11C17/18 ,  G11C13/00 ,  G11C7/10

Abstract: In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.

公开(公告)号：US20150255136A1

公开(公告)日：2015-09-10

申请号：US14714796

申请日：2015-05-18

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Wolf Allers ,  Mihail Jefremow

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1659 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.

Abstract translation: 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 在一个示例中，用于读取存储器单元的系统包括感测路径和反向路径。 通过感测路径提供参考电流，并且通过感测路径中的第一采样元件进行采样，并且通过反向感测路径提供来自存储器单元的单元电流，并且经由反向感测路径中的第二采样元件进行采样 。 随后，存储器单元与反向感测路径断开，通过感测路径提供单元电流，参考源与感测路径断开，并通过反向感测路径提供参考电流。 然后，输出电平由电池和参考电流根据采样的参考和采样单元电流工作来确定。

公开(公告)号：US20130099289A1

公开(公告)日：2013-04-25

申请号：US13711404

申请日：2012-12-11

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC: H01L23/52

CPC classification number: H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract translation: 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。

公开(公告)号：US11062761B1

公开(公告)日：2021-07-13

申请号：US16740893

申请日：2020-01-13

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Wolf Allers ,  Christian Peters

IPC: G11C11/4094 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4097

Abstract: A position of a memory cell to be accessed within a memory field of a memory device is identified. A region associated with the memory field within which the position is located is identified. A compensation parameter comprising a fixed electric step value for the region is identified. The compensation parameter may be selected from a set of compensation parameters or may be calculated based upon the position of the memory cell. The compensation parameter is applied to an action performed on a line connected to the memory cell during the access of the memory cell.

公开(公告)号：US09558797B2

公开(公告)日：2017-01-31

申请号：US15095482

申请日：2016-04-11

Applicant: Infineon Technologies AG

Inventor： Giacomo Curatolo ,  Wolf Allers

IPC: G11C7/22 ,  G11C7/12 ,  G11C5/14 ,  G11C7/20

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/20

Abstract: A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.

Abstract translation: 公开了一种用于控制阵列单元中的电流的方法和装置。 该方法包括将电源电压施加到晶体管的第一接入点，将晶体管的第二接入点预先充电至预定电压，将控制电压施加到晶体管的第三接入点，以及将晶体管的第二接入点 晶体管导通晶体管，其导致电流流过连接到晶体管的阵列单元。

公开(公告)号：US08502276B2

公开(公告)日：2013-08-06

申请号：US13711404

申请日：2012-12-11

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC: H01L23/52

CPC classification number: H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract translation: 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。

公开(公告)号：US11907044B2

公开(公告)日：2024-02-20

申请号：US17473905

申请日：2021-09-13

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Wolf Allers

IPC: G06F11/00 ,  G11C7/06 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/004 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/06

Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.

公开(公告)号：US20210174868A1

公开(公告)日：2021-06-10

申请号：US17117713

申请日：2020-12-10

Applicant: Infineon Technologies AG

Inventor： David MUELLER ,  Wolf Allers ,  Christian Peters

IPC: G11C13/00 ,  G11C7/10

Abstract: In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.