公开(公告)号：US20190355642A1

公开(公告)日：2019-11-21

申请号：US16335527

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Chi-Mon Chen ,  Robert Alan May ,  Amanda E. Schuckman ,  Wei-Lun Kane Jen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/367 ,  H01L23/538 ,  H01L21/56

Abstract: Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

公开(公告)号：US09788416B2

公开(公告)日：2017-10-10

申请号：US14778987

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： Wei-Lun Kane Jen ,  Padam Jain ,  Dilan Seneviratne ,  Chi-Mon Chen

IPC: H01L23/13 ,  H05K1/02 ,  H01L21/02 ,  H01L23/12 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H01L25/065 ,  H05K1/03

CPC classification number: H05K1/0271 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/02035 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0014 ,  H05K3/0044 ,  H05K2201/0191 ,  H05K2201/05 ,  H05K2203/0278 ,  H05K2203/085 ,  H01L2924/00

Abstract: Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.

公开(公告)号：US10916486B2

公开(公告)日：2021-02-09

申请号：US16335527

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Chi-Mon Chen ,  Robert Alan May ,  Amanda E. Schuckman ,  Wei-Lun Kane Jen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L21/56 ,  H01L23/367

Abstract: Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

公开(公告)号：US20160329274A1

公开(公告)日：2016-11-10

申请号：US14778987

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： Wei-Lun Kane Jen ,  Padam Jain ,  Dilan Seneviratne ,  Chi-Mon Chen

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00

CPC classification number: H05K1/0271 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/02035 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0014 ,  H05K3/0044 ,  H05K2201/0191 ,  H05K2201/05 ,  H05K2203/0278 ,  H05K2203/085 ,  H01L2924/00

Abstract: Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.

Abstract translation: 所公开的实施例包括用于半导体封装的多层衬底。 衬底可以包括第一层，第一层具有xy平面，第一侧上的各个位置具有低于第一侧面xy平面的第一侧面距离，第二侧面具有第二面xy平面和各个位置 在第二侧上可以具有在第二侧面xy平面下方的第二侧面距离; 以及第二层，其具有耦合到第一层的第二侧的第一侧和与第二层的第一侧相对的第二侧，其中第二层上的各个位置处的第二层的厚度可以由 第一侧距离加上第二边距离。 可以描述和/或要求保护其他实施例。