公开(公告)号：US09257380B2

公开(公告)日：2016-02-09

申请号：US14624873

申请日：2015-02-18

Applicant: Intel Corporation

Inventor： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L21/02 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

公开(公告)号：US09232686B2

公开(公告)日：2016-01-05

申请号：US14227929

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Kemal Aygun ,  Daniel N. Sobieski ,  Drew W. Delaney

IPC: H05K7/00 ,  H05K9/00 ,  H05K1/02 ,  C23C14/34 ,  H05K3/00 ,  C23C14/14

CPC classification number: H05K3/007 ,  C23C14/14 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0219 ,  H05K1/185 ,  H05K3/02 ,  H05K3/30 ,  H05K3/4682 ,  H05K2201/0715 ,  H05K2203/1469 ,  H05K2203/308 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.

Abstract translation: 一种包括模具的装置，包括具有限定模具的厚度的接触点和侧壁的装置侧; 耦合到管芯的积聚载体，所述堆积载体包括多个图案化导电材料和绝缘材料的交替层，其中图案化导电材料层中的至少一层耦合到 死; 以及包括设置在管芯上的导电材料和积聚载体的一部分的干涉屏蔽。 该装置可以连接到印刷电路板。 一种方法，包括在包括图案化导电材料和绝缘材料的多个交替层的模具的器件侧附近形成堆积载体; 以及在积聚载体的一部分上形成干涉屏蔽。

公开(公告)号：US20150179559A1

公开(公告)日：2015-06-25

申请号：US14624873

申请日：2015-02-18

Applicant: Intel Corporation

Inventor： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  H01L23/482 ,  H01L23/522

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：US08987065B2

公开(公告)日：2015-03-24

申请号：US14090461

申请日：2013-11-26

Applicant: Intel Corporation

Inventor： Ravi K. Nailla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：US10375832B2

公开(公告)日：2019-08-06

申请号：US14956214

申请日：2015-12-01

Applicant: Intel Corporation

Inventor： Digvijay A. Raorane ,  Kemal Aygun ,  Daniel N. Sobieski ,  Drew W. Delaney

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/02 ,  H05K3/30 ,  H05K3/46 ,  C23C14/14 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.

公开(公告)号：US09627227B2

公开(公告)日：2017-04-18

申请号：US14465325

申请日：2014-08-21

Applicant: Intel Corporation

Inventor： Pramod Malatkar ,  Drew W. Delaney

IPC: H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.