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公开(公告)号:US10912494B2
公开(公告)日:2021-02-09
申请号:US15780226
申请日:2016-08-10
Applicant: Intel Corporation
Inventor: Ke Han , Dong Wang , He Han , Dror Lederman , Lev Lavy , Yehiel Shilo
Abstract: A sensor interface circuit enables signal reconstruction on data received from a sensor prior to sending the data to various sensor clients. Multiple sensor clients have different frequencies configured to receive sensor data. The sensor interface circuit performs signal reconstructions including data interpolation to generate interpolated data signal having frequencies corresponding to the different frequencies configured for the different sensor clients. Signal reconstruction can also include filtering the data. The sensor interface circuit sends the reconstructed data to the multiple clients in accordance with their different frequencies.
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公开(公告)号:US10163508B2
公开(公告)日:2018-12-25
申请号:US15055153
申请日:2016-02-26
Applicant: Intel Corporation
Inventor: Woojong Han , Mohamed Arafa , Brian S. Morris , Mani Prakash , James K. Pickett , John K. Grooms , Bruce Querbach , Edward L Payton , Dong Wang
Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20170249991A1
公开(公告)日:2017-08-31
申请号:US15055153
申请日:2016-02-26
Applicant: Intel Corporation
Inventor: Woojong Han , Mohamed Arafa , Brian S. Morris , Mani Prakash , James K. Pickett , John K. Grooms , Bruce Querbach , Edward L Payton , Dong Wang
CPC classification number: G11C14/0009 , G11C5/02 , G11C5/025 , G11C5/141 , G11C11/005
Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20160093377A1
公开(公告)日:2016-03-31
申请号:US14498480
申请日:2014-09-26
Applicant: Intel Corporation
Inventor: Mani Prakash , Edward L. Payton , John K. Grooms , Dimitrios Ziakas , Mohammed Arafa , Raj K. Ramanujan , Dong Wang
IPC: G11C14/00 , G11C7/10 , G11C11/406
CPC classification number: G11C14/0018 , G11C5/04 , G11C7/1072 , G11C11/40615
Abstract: Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了包括存储器模块的存储器模块,控制器和电子设备。 在一个实施例中,存储器模块包括非易失性存储器和到易失性存储器总线的接口,至少一个用于从主机平台接收电力的输入电源轨,以及控制器,其包括至少部分地包括硬件逻辑的逻辑,以将 从输入电源轨从输入电压到不同于输入电压的至少一个输出电压的电力。 还公开并要求保护其他实施例。
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公开(公告)号:US11526205B2
公开(公告)日:2022-12-13
申请号:US15734820
申请日:2018-12-31
Applicant: Intel Corporation
Inventor: Ke Han , Mingqiu Sun , Dong Wang , Prakash Iyer , Stephan Jourdan , Andrzej Mialkowski
IPC: G06F1/32 , G06F9/48 , G06F1/329 , G06F1/3296
Abstract: Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.
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公开(公告)号:US20210232199A1
公开(公告)日:2021-07-29
申请号:US15734820
申请日:2018-12-31
Applicant: Intel Corporation
Inventor: Ke Han , Mingqiu Sun , Dong Wang , Prakash Iyer , Stephan Jourdan , Andrzej Mialkowski
IPC: G06F1/329 , G06F1/3296 , G06F9/48
Abstract: Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.
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公开(公告)号:US20230114206A1
公开(公告)日:2023-04-13
申请号:US17990309
申请日:2022-11-18
Applicant: Intel Corporation
Inventor: Ke Han , Mingqiu Sun , Dong Wang , Prakash Iyer , Stephan Jourdan , Andrzej Mialkowski
IPC: G06F1/329 , G06F1/3296 , G06F9/48
Abstract: Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.
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公开(公告)号:US10509748B2
公开(公告)日:2019-12-17
申请号:US15577658
申请日:2016-12-30
Applicant: INTEL CORPORATION
Inventor: Ke Han , Dong Wang , Qin Duan , Xiaodong Cai , Lu Wang
Abstract: Memory sharing techniques are provided for offloading an application from a host processor to an integrated sensor hub (ISH). A methodology implementing the techniques according to an embodiment includes allocating a shared region of memory to be accessed by the host processor and by the ISH, in connection with the execution of a location application. The method also includes storing a location database in the shared region of memory. The location database is divided into segments, where each segment is associated with an area, for example, defined by a range of latitudes and longitudes. The method further includes transferring, through a direct memory access (DMA), one or more of the segments between the shared memory region and a second memory associated with the ISH. The method further includes executing at least a portion of the location application on the ISH, based on the data segments stored in the second memory.
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