公开(公告)号：US09472515B2

公开(公告)日：2016-10-18

申请号：US14205093

申请日：2014-03-11

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Teodora Ossiander ,  Frank Zudock ,  Christian Geissler

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L24/11 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76871 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/821 ,  H01L2224/82105 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2224/03

Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及组装集成电路封装的方法。 在实施例中，该方法可以包括提供具有未图案化钝化层的晶片以防止嵌入晶片中的金属导体的腐蚀。 该方法还可以包括将绝缘材料层压在钝化层上以形成电介质层，并选择性地去除电介质材料以在电介质层中形成空隙。 这些空隙可以露出设置在金属导体上的钝化层的部分。 该方法可以包括去除钝化层的部分以露出金属导体。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20170103956A1

公开(公告)日：2017-04-13

申请号：US15294499

申请日：2016-10-14

Applicant: Intel Corporation

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Teodora Ossiander ,  Frank Zudock ,  Christian Geissler

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L24/11 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76871 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/821 ,  H01L2224/82105 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2224/03

Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

公开(公告)号：US10157869B2

公开(公告)日：2018-12-18

申请号：US15294499

申请日：2016-10-14

Applicant: Intel Corporation

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Teodora Ossiander ,  Frank Zudock ,  Christian Geissler

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/525

Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.