公开(公告)号：US20200004541A1

公开(公告)日：2020-01-02

申请号：US16021974

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Karthik SANKARANARAYANAN ,  Stephen J. TARSA ,  Gautham N. CHINYA ,  Helia NAEIMI

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

公开(公告)号：US20190095328A1

公开(公告)日：2019-03-28

申请号：US15717934

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Helia NAEIMI ,  Qi ZENG

IPC: G06F12/0811 ,  G06F12/128 ,  G06F12/0888

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/621

Abstract: Provided are an apparatus, system, integrated circuit die, and method for caching data in a hierarchy of caches. A first cache line in a first level cache having modified data for an address is processed. Each cache line of cache lines in the first level cache store data for one of a plurality of addresses stored in multiple cache lines of a second level cache. A second cache line in the second level cache is selected and a determination is made of a number of corresponding bits in the first cache line and the second cache line that are different. Bits in the first cache line that are different from the corresponding bits in the second cache line are written to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.

公开(公告)号：US20180025764A1

公开(公告)日：2018-01-25

申请号：US15676964

申请日：2017-08-14

Applicant: INTEL CORPORATION

Inventor： Helia NAEIMI ,  Shih-Lien L. LU ,  Shigeki TOMISHIMA

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

Abstract: In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.

公开(公告)号：US20190095349A1

公开(公告)日：2019-03-28

申请号：US15717933

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Helia NAEIMI ,  Qi ZENG

IPC: G06F12/128 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/128 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/121 ,  G06F12/123 ,  G06F2212/283 ,  G06F2212/621

Abstract: Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory device. An incoming cache line is read from the second memory device. A plurality of cache lines in the first memory device are processed to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line. Bits from the incoming cache line that are different from the bits in the eviction cache line are written to the eviction cache line in the first memory device.

公开(公告)号：US20170178708A1

公开(公告)日：2017-06-22

申请号：US15371122

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Wei WU ,  Shih-Lien LU ,  James W. TSCHANZ ,  Georgios PANAGOPOULOS ,  Helia NAEIMI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

公开(公告)号：US20160188890A1

公开(公告)日：2016-06-30

申请号：US14583513

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： Helia NAEIMI ,  Shigeki TOMISHIMA ,  Shih-Lien L. LU

IPC: G06F21/62 ,  G06F12/14 ,  G06F21/79 ,  G06F12/02

CPC classification number: G06F21/62 ,  G06F12/0246 ,  G06F12/1433 ,  G06F21/34 ,  G06F21/74 ,  G06F21/77 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2221/2143 ,  H04W12/1206

Abstract: In one embodiment, a device containing sensitive information may be placed in a data security mode. In such a data security mode, certain activities may trigger the partial or full erasure of the sensitive date before the data can be retrieved by an unauthorized user. In one embodiment, the data security mode may be a “park” mode in which unauthorized physical movement of the device triggers the partial or full erasure of the sensitive data stored in a nonvolatile memory before the data can be retrieved by an unauthorized user. In another aspect of the present description, the earth's magnetic field may be used to detect movement of a device in the park mode, and may be used to power the erasure of sensitive data as the device is moved relative to the earth's magnetic field. Other aspects are described herein.

Abstract translation: 在一个实施例中，可以将包含敏感信息的设备置于数据安全模式中。 在这样的数据安全模式中，某些活动可能会触发敏感日期的部分或全部擦除，然后才能由未经授权的用户检索数据。 在一个实施例中，数据安全模式可以是“驻留”模式，其中在未经授权的用户可以检索数据之前，设备的未经授权的物理移动触发存储在非易失性存储器中的敏感数据的部分或全部擦除。 在本说明书的另一方面，地球磁场可用于检测驻留模式中的装置的移动，并且可以用于在设备相对于地球磁场移动时对敏感数据的擦除提供动力。 本文描述了其它方面。

公开(公告)号：US20160188495A1

公开(公告)日：2016-06-30

申请号：US14583518

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： Helia NAEIMI ,  Shigeki TOMISHIMA ,  Shih-Lien L. LU

IPC: G06F12/14 ,  G06F12/02 ,  G11C16/34 ,  G11C14/00 ,  G11C11/16 ,  G11C16/10

CPC classification number: G06F12/1425 ,  G06F12/0246 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/7205 ,  G06F2212/7209 ,  G06F2221/2143 ,  G11C5/148 ,  G11C7/24 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1695 ,  G11C11/1697 ,  G11C14/0081 ,  G11C16/105 ,  G11C16/107 ,  G11C16/14 ,  G11C16/16 ,  G11C16/22 ,  G11C16/3486

Abstract: One aspect of the present description provides for automatically erasing at least a portion of a memory such as a nonvolatile memory, for example, of a device in response to a detected event such as a power shutdown or power-up process, for example. In one embodiment, an on-board erasure assistance device such as an electro-magnet, for example, facilitates sensitive data erasure. In accordance with another aspect of the present description, a satisfactory level of sensitive data erasure may be achieved by resetting a portion of the bits of the sensitive data, instead of resetting all the bits of sensitive data. In one embodiment, the bits which are reset to erase sensitive data may be randomly distributed over a subarray. Other aspects are described herein.

Abstract translation: 本说明书的一个方面提供了例如响应于检测到的事件（例如电源关闭或上电过程）来自动擦除诸如设备的非易失性存储器的存储器的至少一部分。 在一个实施例中，诸如电磁体的车载擦除辅助装置例如有利于敏感的数据擦除。 根据本说明书的另一方面，可以通过复位敏感数据的位的一部分而不是重置敏感数据的所有位来实现令人满意的敏感数据擦除级别。 在一个实施例中，复位以擦除敏感数据的位可以随机分布在子阵列上。 本文描述了其它方面。