公开(公告)号：US12197004B2

公开(公告)日：2025-01-14

申请号：US17358912

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Harel Frish ,  John Heck ,  Randal Appleton ,  Stefan Meister ,  Haisheng Rong ,  Joshua Keener ,  Michael Favaro ,  Wesley Harrison ,  Hari Mahalingam ,  Sergei Sochava

IPC: G02B6/12 ,  G02B6/122 ,  H01S5/026

Abstract: Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.

公开(公告)号：US20240345319A1

公开(公告)日：2024-10-17

申请号：US18750754

申请日：2024-06-21

Applicant: Intel Corporation

Inventor： Hari Mahalingam ,  Harel Frish ,  Sean McCargar ,  Joshua Keener ,  Shane Yerkes ,  John Heck ,  Ling Liao

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/26 ,  G02B6/30

CPC classification number: G02B6/1228 ,  G02B6/13 ,  G02B6/26 ,  G02B6/305

Abstract: Embodiments of the present disclosure are directed to low numerical aperture (NA) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. In embodiments, the optical couplers may be positioned on a silicon substrate proximate to V-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. Other embodiments may be described and/or claimed.

公开(公告)号：US12019270B2

公开(公告)日：2024-06-25

申请号：US17004429

申请日：2020-08-27

Applicant: Intel Corporation

Inventor： Hari Mahalingam ,  Harel Frish ,  Sean McCargar ,  Joshua Keener ,  Shane Yerkes ,  John Heck ,  Ling Liao

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/26 ,  G02B6/30

CPC classification number: G02B6/1228 ,  G02B6/13 ,  G02B6/26 ,  G02B6/305

Abstract: Embodiments of the present disclosure are directed to low numerical aperture (NA) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. In embodiments, the optical couplers may be positioned on a silicon substrate proximate to V-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. Other embodiments may be described and/or claimed.

公开(公告)号：US11908687B2

公开(公告)日：2024-02-20

申请号：US17563968

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  John Heck ,  Thomas Sounart ,  Harel Frish ,  Sansaptak Dasgupta

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8222

CPC classification number: H01L21/02458 ,  H01L21/02389 ,  H01L21/02452 ,  H01L21/8222 ,  H01L21/823418

Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US20240004129A1

公开(公告)日：2024-01-04

申请号：US17853732

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  John Heck ,  Pushkar Sharad Ranade ,  Ravindranath Vithal Mahajan ,  Thomas Liljeberg ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: G02B6/12 ,  G02B6/13 ,  H01L25/16 ,  H01L23/00

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  G02B6/13 ,  H01L25/167 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in an array; and a plurality of photonic integrated circuit (PIC) dies, each PIC die having waveguides. Adjacent microelectronic sub-assemblies are coupled to one of the PIC dies by interconnects such that any one PIC die is coupled to more than two adjacent microelectronic sub-assemblies, and the microelectronic sub-assemblies coupled to each PIC die in the plurality of PIC dies are communicatively coupled by the waveguides in the PIC die. Each microelectronic sub-assembly comprises: an interposer integrated circuit (IC) die comprising one or more electrical controller circuit proximate to at least one edge of the interposer IC die; a first plurality of IC dies coupled to a first surface of the interposer IC die; and a second plurality of IC dies coupled to an opposing second surface of the interposer IC die.

公开(公告)号：US10996408B2

公开(公告)日：2021-05-04

申请号：US16517159

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： John Heck ,  Harel Frish ,  Reece DeFrees ,  George A. Ghiurcan ,  Hari Mahalingam ,  Pegah Seddighian

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/122

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for an optical coupler including an optical waveguide to guide light to an optical fiber. In embodiments, the optical waveguide includes a tapered segment to propagate the received light to the optical fiber. In embodiments, the tapered segment is buried below a surface of a semiconductor substrate to transition the received light within the semiconductor substrate from a first optical mode to a second optical mode to reduce a loss of light during propagation of the received light from the optical waveguide to the optical fiber. In embodiments, the surface of the semiconductor substrate comprises a bottom planar surface of a silicon photonic chip that includes at least one or more of passive or active photonic components. Other embodiments may be described and/or claimed.

公开(公告)号：US20190041582A1

公开(公告)日：2019-02-07

申请号：US15980103

申请日：2018-05-15

Applicant: Intel Corporation

Inventor： John Heck ,  Hari Mahalingam

IPC: G02B6/30

Abstract: Embodiments may relate to a polymer optical coupler. The polymer optical coupler may include a first portion at least partially coupled to a face of a silicon waveguide. The polymer optical coupler may further include a second portion of the polymer optical coupler that is adjacent to the first portion and which may have a width that is less than a width of the second portion opposite the first portion. Other embodiments may be described and/or claimed.

公开(公告)号：US09575341B2

公开(公告)日：2017-02-21

申请号：US14318604

申请日：2014-06-28

Applicant: Intel Corporation

Inventor： John Heck ,  Jonathan K Doylend ,  David N Hutchison ,  Haisheng Rong ,  Jacob B Sendowski

IPC: G02F1/13 ,  G01S17/42 ,  G01S17/89 ,  G01S7/481 ,  G02B6/12 ,  G01S17/10 ,  G01S17/32

CPC classification number: G02F1/1326 ,  G01S7/4817 ,  G01S17/10 ,  G01S17/325 ,  G01S17/42 ,  G01S17/89 ,  G02B6/12004 ,  G02B2006/12061 ,  G02B2006/12147 ,  G02F1/292

Abstract: A solid state photonics circuit having a liquid crystal (LC) layer for beam steering. The LC layer can provide tuning of an array of waveguides by controlling the application of voltage to the liquid crystal. The application of voltage to the liquid crystal can be controlled to perform beam steering with the light signal based on different tuning in each of the waveguides of the array. The waveguides are disposed in a substrate having an oxide or other insulating layer with an opening. The opening in the oxide layer exposes a portion of a path of the array of waveguides. The waveguides are exposed to the liquid crystal through the oxide opening, which allows the voltage changes to the liquid crystal to tune the optical signals in the waveguides.

Abstract translation: 一种具有用于光束转向的液晶（LC）层的固态光子电路。 LC层可以通过控制对液晶的电压施加来提供波导阵列的调谐。 可以控制对液晶的电压施加，使用基于在阵列的每个波导中的不同调谐的光信号进行光束转向。 波导设置在具有开口的氧化物或其它绝缘层的基板中。 氧化物层中的开口暴露波导阵列的路径的一部分。 波导通过氧化物开口暴露于液晶，这允许液晶的电压改变以调谐波导中的光信号。

公开(公告)号：US08803268B2

公开(公告)日：2014-08-12

申请号：US13871083

申请日：2013-04-26

Applicant: Intel Corporation

Inventor： John Heck ,  Ansheng Liu ,  Michael T. Morse ,  Haisheng Rong

IPC: H01L27/14

CPC classification number: H01L31/02327 ,  G02B6/4214

Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.

Abstract translation: 垂直全内反射（TIR）镜及其制造是通过使用晶体硅蚀刻创建入门轮廓而制成的。 从SOI晶片开始，使用深硅蚀刻来暴露掩埋氧化物层，然后将其湿法蚀刻（在HF中），打开Si器件层的底表面。 然后将该底部硅表面暴露，使得在晶体刻蚀中，所得到的形状是具有刻面的重入梯形。这些刻面可以与平面硅波导结合使用以基于TIR原理向上反射光。 或者，光可以从晶片上方耦合到硅波导中，用于诸如晶片级测试的目的。

公开(公告)号：US12081276B2

公开(公告)日：2024-09-03

申请号：US17133360

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Meer Nazmus Sakib ,  Peicheng Liao ,  Ranjeet Kumar ,  Duanni Huang ,  Haisheng Rong ,  Harel Frish ,  John Heck ,  Chaoxuan Ma ,  Hao Li ,  Ganesh Balamurugan

IPC: H04B10/61

CPC classification number: H04B10/6165 ,  H04B10/612 ,  H04B10/6164

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to coherent optical receivers, including coherent receivers with integrated all-silicon waveguide photodetectors and tunable local oscillators implemented within CMOS technology. Embodiments are also directed to tunable silicon hybrid lasers with integrated temperature sensors to control wavelength. Embodiments are also directed to post-process phase correction of optical hybrid and nested I/Q modulators. Embodiments are also directed to demultiplexing photodetectors based on multiple microrings. In embodiments, all components may be implements on a silicon substrate. Other embodiments may be described and/or claimed.