公开(公告)号：US20220230800A1

公开(公告)日：2022-07-21

申请号：US17713662

申请日：2022-04-05

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Venkata Ramanuja Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US11380609B2

公开(公告)日：2022-07-05

申请号：US15985348

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Jiwei Sun ,  Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US11322290B2

公开(公告)日：2022-05-03

申请号：US16012259

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US11272619B2

公开(公告)日：2022-03-08

申请号：US16321420

申请日：2016-09-02

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Robert A. May ,  Yikang Deng ,  Ji Yong Park ,  Maroun D. Moussallem ,  Amruthavalli P. Alur ,  Sri Ranga Sai Boyapati ,  Lilia May

IPC: H05K1/18 ,  H05K3/42 ,  H01L21/60 ,  H01L27/146 ,  G01J5/20 ,  H05K1/11 ,  H05K3/46

Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

公开(公告)号：US20210273036A1

公开(公告)日：2021-09-02

申请号：US16804317

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Prithwish Chatterjee ,  Haifa Hariri ,  Yikang Deng ,  Sheng C. Li ,  Srinivas Pietambaram

IPC: H01L49/02 ,  H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

公开(公告)号：US10396046B2

公开(公告)日：2019-08-27

申请号：US15859316

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Yikang Deng ,  Robert Sankman

IPC: H01F27/00 ,  H01L23/64 ,  H01L23/00 ,  H01F27/28 ,  H05K1/02

Abstract: Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.

公开(公告)号：US11923307B2

公开(公告)日：2024-03-05

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11696407B2

公开(公告)日：2023-07-04

申请号：US17560004

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Ying Wang ,  Junnan Zhao ,  Cheng Xu ,  Yikang Deng

IPC: H01L23/495 ,  H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00 ,  H05K3/06 ,  H01L23/00

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F27/2804 ,  H01F41/041 ,  H01F41/046 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/422 ,  H01F2017/002 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/1427 ,  H01L2924/19042 ,  H01L2924/19102 ,  H05K3/06 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/072 ,  H05K2203/107

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20230187205A1

公开(公告)日：2023-06-15

申请号：US18165422

申请日：2023-02-07

Applicant: Intel Corporation

Inventor： Ying Wang ,  Chong Zhang ,  Meizi Jiao ,  Junnan Zhao ,  Cheng Xu ,  Yikang Deng

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L21/02422 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L21/76816 ,  H01L23/49827 ,  H01L23/49894

Abstract: Embodiments may relate to a semiconductor package that includes a die and a glass core coupled with the die. The glass core may include a cavity with an interconnect structure therein. The interconnect structure may include pads on a first side that are coupled with the die, and pads on a second side opposite the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US11444042B2

公开(公告)日：2022-09-13

申请号：US16000372

申请日：2018-06-05

Applicant: Intel Corporation

Inventor： Andrew James Brown ,  Ying Wang ,  Chong Zhang ,  Lauren Ashley Link ,  Yikang Deng

IPC: H01L23/64 ,  H01F3/14 ,  H01F27/06 ,  H01F41/02

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line and a magnetic structure around a top surface of the conductive line and side surfaces of the conductive line. The magnetic structure may have a tapered shape that narrows toward the conductive line.