公开(公告)号：US10580899B2

公开(公告)日：2020-03-03

申请号：US15405899

申请日：2017-01-13

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L21/268 ,  H01L29/78 ,  B82Y40/00

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US09680013B2

公开(公告)日：2017-06-13

申请号：US14018867

申请日：2013-09-05

Applicant: INTEL CORPORATION

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Jack T. Kavalieros ,  Martin D. Giles ,  Tahir Ghani ,  Kelin J. Kuhn ,  Markus Kuhn ,  Nancy M. Zelick

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

公开(公告)号：US10985184B2

公开(公告)日：2021-04-20

申请号：US15470832

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Martin D. Giles ,  Tahir Ghani

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/165 ,  H01L21/02

Abstract: Embodiments of the present disclosure relate to non-planar semiconductor device structures having fins. In one embodiment, a semiconductor device includes a substrate, silicon fins positioned on the substrate, and a germanium layer that is epitaxially grown on an upper region of the silicon fins with the silicon fins and the germanium layer forming a body of the semiconductor device.

公开(公告)号：US09595581B2

公开(公告)日：2017-03-14

申请号：US14789856

申请日：2015-07-01

Applicant: Intel Corporation

Inventor： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L27/12 ,  H01L27/092 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

公开(公告)号：US12205955B2

公开(公告)日：2025-01-21

申请号：US17187284

申请日：2021-02-26

Applicant: INTEL CORPORATION

Inventor： Martin D. Giles ,  Tahir Ghani

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

公开(公告)号：US20170200744A1

公开(公告)日：2017-07-13

申请号：US15470832

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Martin D. Giles ,  Tahir Ghani

IPC: H01L27/12 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present disclosure relate to non-planar semiconductor device structures having fins. In one embodiment, a semiconductor device includes a substrate, silicon fins positioned on the substrate, and a germanium layer that is epitaxially grown on an upper region of the silicon fins with the silicon fins and the germanium layer forming a body of the semiconductor device.