公开(公告)号：US10249490B2

公开(公告)日：2019-04-02

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. Chau ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Niloy Mukherjee ,  Nancy M. Zelick ,  Gilbert Dewey ,  Willy Rachmady ,  Marko Radosavljevic ,  Van H. Le ,  Ravi Pillarisetty ,  Sansaptak Dasgupta

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US10756198B2

公开(公告)日：2020-08-25

申请号：US15679077

申请日：2017-08-16

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC: H01L29/40 ,  H01L29/51 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/324 ,  H01L51/52 ,  H01L31/0224 ,  H01L21/04 ,  H01L51/10 ,  H01L51/44 ,  H01L29/45 ,  H01L45/00 ,  H01L33/00 ,  H01B1/12 ,  H01L33/40

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

公开(公告)号：US20150001644A1

公开(公告)日：2015-01-01

申请号：US14490581

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC: H01L29/51 ,  H01L21/768 ,  H01L21/324 ,  H01L21/285

CPC classification number: H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

Abstract translation: 使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。 中间层可以是稀土氧化物。 中间层可以是离子半导体。 金属阻挡膜可以设置在中间层和金属耦合器之间。 中间层可以是金属阻挡膜和半导体基板的热处理组合。 形成中间层的方法可以包括对中间层进行分级。 计算系统包括中间层。

公开(公告)号：US11631737B2

公开(公告)日：2023-04-18

申请号：US15529481

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Sanaz K. Gardner ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Chandra S. Mohapatra ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Nancy M. Zelick ,  Tahir Ghani

IPC: H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/04

Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

公开(公告)号：US09768269B2

公开(公告)日：2017-09-19

申请号：US14490581

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/469 ,  H01L23/48 ,  H01L29/40 ,  H01L23/52 ,  H01L29/51 ,  H01L21/285 ,  H01L23/485 ,  H01L23/532 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L21/768 ,  H01L51/52 ,  H01L31/0224 ,  H01L21/04 ,  H01L51/10 ,  H01L51/44 ,  H01L29/45 ,  H01L45/00 ,  H01L33/00 ,  H01B1/12 ,  H01L33/40

CPC classification number: H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

公开(公告)号：US09680013B2

公开(公告)日：2017-06-13

申请号：US14018867

申请日：2013-09-05

Applicant: INTEL CORPORATION

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Jack T. Kavalieros ,  Martin D. Giles ,  Tahir Ghani ,  Kelin J. Kuhn ,  Markus Kuhn ,  Nancy M. Zelick

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

公开(公告)号：US09640537B2

公开(公告)日：2017-05-02

申请号：US14915185

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. Chau ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Niloy Mukherjee ,  Nancy M. Zelick ,  Gilbert Dewey ,  Willy Rachmady ,  Marko Radosavljevic ,  Van H. Le ,  Ravi Pillarisetty ,  Sansaptak Dasgupta

IPC: H01L21/00 ,  H01L31/072 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US09391181B2

公开(公告)日：2016-07-12

申请号：US13723563

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van H. Le ,  Robert S. Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy M. Zelick

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L29/78 ,  H01L29/74

CPC classification number: H01L29/7391 ,  H01L29/0676 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66356 ,  H01L29/66393 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7436 ,  H01L29/785

Abstract: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.

Abstract translation: 一个实施例涉及在衬底上形成EPI膜，其中EPI膜具有与衬底不同的晶格常数。 EPI膜和衬底可以包括不同的材料以共同形成具有例如Si和/或SiGe衬底和III-V或IV膜的异质外延装置。 EPI膜可以是多个EPI层或膜中的一个，并且膜可以包括彼此不同的材料并且可以直接彼此接触。 此外，在掺杂浓度和/或掺杂极性方面，多个EPI层可以与另一个不同地被掺杂。 一个实施例包括产生水平取向的异质外延结构。 另一实施例包括垂直取向的异质外延结构。 异质外延结构可以包括例如双极结型晶体管，异质结双极晶体管，晶闸管和隧道场效应晶体管等。 本文描述了其它实施例。