公开(公告)号：US09608042B2

公开(公告)日：2017-03-28

申请号：US15017552

申请日：2016-02-05

申请人： INTEL CORPORATION

发明人： Fabio Pellizzer ,  Giulio Albini ,  Stephen W. Russell ,  Max F. Hineman ,  Sanjay Rangan

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09559146B2

公开(公告)日：2017-01-31

申请号：US14581921

申请日：2014-12-23

申请人： Intel Corporation

发明人： Lequn J. Liu ,  Ugo Russo ,  Max F. Hineman

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1675

摘要： Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了用于虚拟阵列泄漏减少的相变存储器单元注入。 在一个实施例中，一种装置包括多个相变存储器（PCM）元件，其中多个PCM元件中的各个PCM元件是包括底部电极层，设置在底部电极层上的选择器件层， 设置在选择器件层上的中间电极层，设置在中间电极层上的相变材料层和设置在相变材料层上的顶部电极层，其中相变材料层掺杂有杂质 减少虚拟细胞的细胞泄漏。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160233271A1

公开(公告)日：2016-08-11

申请号：US15017552

申请日：2016-02-05

申请人： INTEL CORPORATION

发明人： Fabio Pellizzer ,  Giulio Albini ,  Stephen W. Russell ,  Max F. Hineman ,  Sanjay Rangan

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了增加相变存储器元件的电热隔离和相关技术的电极配置。 在一个实施例中，一种装置包括多个相变存储器（PCM）元件，其中多个PCM元件中的各个PCM元件包括相变材料层，设置在相变材料层上的第一电极层和 与所述相变材料层直接接触，以及设置在所述第一电极层上并与所述第一电极层直接接触的第二电极层。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160181324A1

公开(公告)日：2016-06-23

申请号：US14581921

申请日：2014-12-23

申请人： Intel Corporation

发明人： Lequn J. Liu ,  Ugo Russo ,  Max F. Hineman

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1675

摘要： Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了用于虚拟阵列泄漏减少的相变存储器单元注入。 在一个实施例中，一种装置包括多个相变存储器（PCM）元件，其中多个PCM元件中的各个PCM元件是包括底部电极层，设置在底部电极层上的选择器件层， 设置在选择器件层上的中间电极层，设置在中间电极层上的相变材料层和设置在相变材料层上的顶部电极层，其中相变材料层掺杂有杂质 减少虚拟细胞的细胞泄漏。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11195575B1

公开(公告)日：2021-12-07

申请号：US16946527

申请日：2020-06-25

申请人： Intel Corporation

发明人： Jaydip Bharatkumar Patel ,  Everardo Flores, III ,  Khaled Hasnat ,  Max F. Hineman

IPC分类号： G11C11/4099 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/02

摘要： A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.

公开(公告)号：US09837604B2

公开(公告)日：2017-12-05

申请号：US15399701

申请日：2017-01-05

申请人： Intel Corporation

发明人： Lequn J. Liu ,  Ugo Russo ,  Max F. Hineman

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1675

摘要： Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.

公开(公告)号：US20170125671A1

公开(公告)日：2017-05-04

申请号：US15399701

申请日：2017-01-05

申请人： Intel Corporation

发明人： Lequn J. Liu ,  Ugo Russo ,  Max F. Hineman

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1675

摘要： Embodiments of the present disclosure describe phase-change memory cell implant for dummy array leakage reduction. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements are dummy cells including a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, and a top electrode layer disposed on the phase-change material layer, wherein the phase-change material layer is doped with an impurity to reduce cell leakage of the dummy cells. Other embodiments may be described and/or claimed.

公开(公告)号：US09299747B1

公开(公告)日：2016-03-29

申请号：US14552205

申请日：2014-11-24

申请人： Intel Corporation

发明人： Fabio Pellizzer ,  Giulio Albini ,  Stephen W. Russell ,  Max F. Hineman ,  Sanjay Rangan

IPC分类号： H01L27/115 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了增加相变存储器元件的电热隔离和相关技术的电极配置。 在一个实施例中，一种装置包括多个相变存储器（PCM）元件，其中多个PCM元件中的各个PCM元件包括相变材料层，设置在相变材料层上的第一电极层和 与所述相变材料层直接接触，以及设置在所述第一电极层上并与所述第一电极层直接接触的第二电极层。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09231202B2

公开(公告)日：2016-01-05

申请号：US13921672

申请日：2013-06-19

申请人： Intel Corporation

发明人： Kiran Pangal ,  Max F. Hineman

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1293 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

摘要： A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.

摘要翻译： 在多层相变交叉点存储器的甲板的位线（BL）层或字线（WL）层之间形成热隔离层，以减轻趋向于作为存储器增加的存储器单元的热问题干扰 尺寸缩小。 本文公开的主题的实施例适用于但不限于固态存储器阵列和固态驱动器。

公开(公告)号：US20210407582A1

公开(公告)日：2021-12-30

申请号：US16946527

申请日：2020-06-25

申请人： Intel Corporation

发明人： Jaydip Bharatkumar Patel ,  Everardo Flores, III ,  Khaled Hasnat ,  Max F. Hineman

IPC分类号： G11C11/4099 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/02

摘要： A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.