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    MEMORY CELLS BASED ON THIN-FILM TRANSISTORS
    1.
    发明申请
    MEMORY CELLS BASED ON THIN-FILM TRANSISTORS 有权

    公开(公告)号：US20220310849A1

    公开(公告)日：2022-09-29

    申请号：US17840186

    申请日：2022-06-14

    Applicant: Intel Corporation

    Inventor： Travis W. LAJOIE ,  Abhishek SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Juan ALZATE VINASCO

    IPC: H01L29/786 ,  H01L29/66 ,  H01L27/108 ,  H01L29/49

    Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

    VERTICAL 1T-1C DRAM ARRAY
    2.
    发明申请
    VERTICAL 1T-1C DRAM ARRAY 有权

    公开(公告)号：US20220165737A1

    公开(公告)日：2022-05-26

    申请号：US17667498

    申请日：2022-02-08

    Applicant: Intel Corporation

    Inventor： Ravi PILLARISETTY ,  Van H. LE ,  Gilbert DEWEY ,  Abhishek A. SHARMA

    IPC: H01L27/108

    Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

    CHANNEL STRUCTURES FOR THIN-FILM TRANSISTORS
    5.
    发明申请
    CHANNEL STRUCTURES FOR THIN-FILM TRANSISTORS 审中-公开

    公开(公告)号：US20200098880A1

    公开(公告)日：2020-03-26

    申请号：US16142045

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： Abhishek SHARMA ,  Cory WEBER ,  Van H. LE ,  Sean MA

    IPC: H01L29/47 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108 ,  H01L27/24

    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

    STACKED THIN FILM TRANSISTORS WITH NANOWIRES
    10.
    发明申请
    STACKED THIN FILM TRANSISTORS WITH NANOWIRES 有权

    公开(公告)号：US20220208991A1

    公开(公告)日：2022-06-30

    申请号：US17695744

    申请日：2022-03-15

    Applicant: Intel Corporation

    Inventor： Seung Hoon SUNG ,  Abhishek A. SHARMA ,  Van H. LE ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Tahir GHANI

    IPC: H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

    Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.

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