公开(公告)号：US20230231809A1

公开(公告)日：2023-07-20

申请号：US18154619

申请日：2023-01-13

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

CPC classification number: H04L47/125 ,  H04L47/62 ,  H04L47/624 ,  H04L47/6255 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US09892086B2

公开(公告)日：2018-02-13

申请号：US15193697

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Rahul Shah ,  Arvind Kumar

IPC: G06F9/44 ,  G06F13/42 ,  G06F12/0831 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/445 ,  H04L12/741 ,  H04L12/46

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

公开(公告)号：US20170083476A1

公开(公告)日：2017-03-23

申请号：US15193697

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Rahul Shah ,  Arvind Kumar

IPC: G06F13/42 ,  G06F13/40 ,  G06F9/445

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

公开(公告)号：US12289239B2

公开(公告)日：2025-04-29

申请号：US18154619

申请日：2023-01-13

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US20240129353A1

公开(公告)日：2024-04-18

申请号：US18393236

申请日：2023-12-21

Applicant: Intel Corporation

Inventor： Amruta Misra ,  Niall McDonnell ,  Mrittika Ganguli ,  Edwin Verplanke ,  Stephen Palermo ,  Rahul Shah ,  Pushpendra Kumar ,  Vrinda Khirwadkar ,  Valerie Parker

IPC: H04L65/612 ,  H04L67/02 ,  H04L67/60

CPC classification number: H04L65/612 ,  H04L67/02 ,  H04L67/60

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. An example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. The example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. The example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. The example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.

公开(公告)号：US20160179730A1

公开(公告)日：2016-06-23

申请号：US14578175

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： William R. Halleck ,  Rahul Shah ,  Venkatraman Iyer

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/124 ,  G06F13/1678 ,  G06F13/4282

Abstract: A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be sent over one or more lanes of a link and is to include at least a portion of a start of data sequence (SDS) to include a predefined sequence and a byte number value. The byte number value is to indicate a number of bytes measured from a preceding control interval.

Abstract translation: 将超级序列发送到另一设备以指示从部分宽度链路状态到另一活动链路状态的转换。 超级序列将通过链路的一个或多个通道发送，并且包括数据序列（SDS）的起始的至少一部分以包括预定义的序列和字节数值。 字节数值表示从前一个控制间隔测量的字节数。

公开(公告)号：US20150067207A1

公开(公告)日：2015-03-05

申请号：US14538897

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Rahul Shah ,  Arvind Kumar

IPC: G06F13/42 ,  G06F9/30

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

Abstract translation: 串行数据链路在链路初始化期间进行调整。 链路的适应包括从远程代理接收伪随机二进制序列（PRBS），分析PRBS以识别数据链路的特性，以及生成描述特征的度量数据。

公开(公告)号：US11575607B2

公开(公告)日：2023-02-07

申请号：US17018809

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US20210075730A1

公开(公告)日：2021-03-11

申请号：US17018809

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L12/803 ,  H04L12/863

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US09378171B2

公开(公告)日：2016-06-28

申请号：US13976971

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Rahul Shah ,  Arvind Kumar

IPC: G06F9/46 ,  G06F13/40 ,  G06F12/08 ,  G06F13/42 ,  G06F9/30 ,  H04L12/933 ,  H04L12/741 ,  G06F9/44

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

Abstract translation: 串行数据链路在链路初始化期间进行调整。 链路的适应包括从远程代理接收伪随机二进制序列（PRBS），分析PRBS以识别数据链路的特性，以及生成描述特征的度量数据。