公开(公告)号：US20160133691A1

公开(公告)日：2016-05-12

申请号：US14534816

申请日：2014-11-06

Applicant: Intermolecular, Inc.

Inventor： Prashant B. Phatak ,  Hanhong Chen ,  Tony P. Chiang ,  Chien-Lan Hsueh ,  Monica Mathur

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/60

Abstract: Steps are taken to ensure that the bulk dielectric layer exhibits a crystalline phase before the deposition of a second electrode layer. The crystalline phase of the bulk dielectric layer facilitates the crystallization of the second electrode layer at lower temperature during a subsequent anneal treatment. In some embodiments, one or more interface layers are inserted between the bulk dielectric layer and the first electrode layer and/or the second electrode layer. The interface layers may act as an oxygen sink, facilitate the crystallization of the electrode layer at lower temperature during a subsequent anneal treatment, or provide barriers to leakage current through the film stack.

Abstract translation: 采取步骤以确保在沉积第二电极层之前体积电介质层呈现结晶相。 在随后的退火处理期间，体电介质层的结晶相有助于在较低温度下第二电极层的结晶。 在一些实施例中，一个或多个界面层插入在体电介质层和第一电极层和/或第二电极层之间。 界面层可以充当氧气沉淀器，在随后的退火处理期间促进电极层在较低温度下的结晶，或者提供通过膜堆叠的漏电流的障碍。

公开(公告)号：US09318531B1

公开(公告)日：2016-04-19

申请号：US14516273

申请日：2014-10-16

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Mark Clark

IPC: H01L27/24 ,  H01L29/267 ,  H01L29/45 ,  H01L29/24

CPC classification number: H01L27/2409 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/224 ,  H01L27/2463 ,  H01L45/16

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a silicon carbide/silicon nitride nanolaminate stack. The semiconductor layer of the selector element can include a silicon carbon nitride/silicon nitride nanolaminate stack. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择器元件的半导体层可以包括碳化硅/氮化硅纳米层压体叠层。 选择元件的半导体层可以包括硅氮化硅/氮化硅纳米层叠体。 MSM的导电材料可以包括钨，氮化钛，碳或它们的组合。

公开(公告)号：US08865484B2

公开(公告)日：2014-10-21

申请号：US13727237

申请日：2012-12-26

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L21/66

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US20160111471A1

公开(公告)日：2016-04-21

申请号：US14516273

申请日：2014-10-16

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Mark Clark

IPC: H01L27/24 ,  H01L29/45 ,  H01L29/24 ,  H01L29/267

CPC classification number: H01L27/2409 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/224 ,  H01L27/2463 ,  H01L45/16

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a silicon carbide/silicon nitride nanolaminate stack. The semiconductor layer of the selector element can include a silicon carbon nitride/silicon nitride nanolaminate stack. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.

Abstract translation: 公开了适用于非易失性存储器件应用的选择元件。 选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。 选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。 选择器元件的半导体层可以包括碳化硅/氮化硅纳米层压体叠层。 选择元件的半导体层可以包括硅氮化硅/氮化硅纳米层叠体。 MSM的导电材料可以包括钨，氮化钛，碳或它们的组合。

公开(公告)号：US20160099304A1

公开(公告)日：2016-04-07

申请号：US14507462

申请日：2014-10-06

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur

IPC: H01L49/02

CPC classification number: H01L28/75 ,  H01L27/10805 ,  H01L28/65

Abstract: A capacitor stack includes a base bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. A molybdenum nitride or a molybdenum oxy-nitride layer is formed above the dielectric layer. A fourth top electrode layer is formed above the third top electrode layer. The base top electrode layer includes a conductive metal nitride material.

Abstract translation: 电容器堆叠包括包括导电金属氮化物材料的基底电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 在电介质层上方形成氮化钼或氮氧化钼层。 第四上电极层形成在第三顶电极层的上方。 基极电极层包括导电金属氮化物材料。

公开(公告)号：US08962354B2

公开(公告)日：2015-02-24

申请号：US14491407

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L21/66 ,  H01L49/02 ,  C23C14/22 ,  C23C16/455 ,  H01L29/51

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US20150010705A1

公开(公告)日：2015-01-08

申请号：US14491407

申请日：2014-09-19

Applicant: Intermolecular, Inc.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L49/02 ,  C23C16/455 ,  H01L29/51 ,  C23C14/22

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

公开(公告)号：US20140179033A1

公开(公告)日：2014-06-26

申请号：US13727237

申请日：2012-12-26

Applicant: INTERMOLECULAR, INC.

Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

IPC: H01L21/66

CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。