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    Methods for forming templated materials
    1.
    发明授权
    Methods for forming templated materials 有权
    形成模板材料的方法

    公开(公告)号：US08962354B2

    公开(公告)日：2015-02-24

    申请号：US14491407

    申请日：2014-09-19

    Applicant: Intermolecular, Inc.

    Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

    IPC: H01L21/66 ,  H01L49/02 ,  C23C14/22 ,  C23C16/455 ,  H01L29/51

    CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

    Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

    Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

    Methods for Forming Templated Materials
    2.
    发明申请
    Methods for Forming Templated Materials 有权
    形成模板材料的方法

    公开(公告)号：US20150010705A1

    公开(公告)日：2015-01-08

    申请号：US14491407

    申请日：2014-09-19

    Applicant: Intermolecular, Inc.

    Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

    IPC: H01L49/02 ,  C23C16/455 ,  H01L29/51 ,  C23C14/22

    CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

    Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

    Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

    Surface treatment to improve resistive-switching characteristics
    3.
    发明授权
    Surface treatment to improve resistive-switching characteristics 有权
    表面处理提高电阻开关特性

    公开(公告)号：US08872151B2

    公开(公告)日：2014-10-28

    申请号：US13896955

    申请日：2013-05-17

    Applicant: Intermolecular Inc.

    Inventor： Michael Miller ,  Tony P. Chiang ,  Xiying Costa ,  Tanmay Kumar ,  Prashant B Phatak ,  April Schricker

    IPC: H01L29/02 ,  H01L47/00

    CPC classification number: H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

    Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元结构的方法。 通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。 例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。 在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

    Methods for Forming Templated Materials
    4.
    发明申请
    Methods for Forming Templated Materials 有权
    形成模板材料的方法

    公开(公告)号：US20140179033A1

    公开(公告)日：2014-06-26

    申请号：US13727237

    申请日：2012-12-26

    Applicant: INTERMOLECULAR, INC.

    Inventor： Monica Mathur ,  Michael Miller ,  Prashant B. Phatak

    IPC: H01L21/66

    CPC classification number: H01L28/40 ,  C23C14/228 ,  C23C16/45525 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L29/517

    Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.

    Abstract translation: 形成层的方法可以包括在衬底上限定多个离散位置隔离区（SIR），在离散SIR之一上形成第一层，在第一层上形成第二层，测量晶格参数或电性质 用于形成第一层的工艺参数以不同离散SIR之间的组合方式变化，以探索可能导致对期望晶体结构的第二层的适当晶格匹配的可能层。

    Resistive switching memory element including doped silicon electrode
    5.
    发明授权
    Resistive switching memory element including doped silicon electrode 有权
    电阻式开关存储元件包括掺杂硅电极

    公开(公告)号：US08698121B2

    公开(公告)日：2014-04-15

    申请号：US13935388

    申请日：2013-07-03

    Applicant: Intermolecular, Inc.

    Inventor： Prashant B. Phatak ,  Tony P. Chiang ,  Michael Miller ,  Wen Wu

    IPC: H01L47/00

    CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: A resistive switching memory is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching using unipolar or bipolar switching voltages for switching from a low resistance state to a high resistance state and vice versa.

    Abstract translation: 描述了一种电阻式开关存储器，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特（eV）之间的金属氧化物 在第一电极和第二电极之间，金属氧化物层使用单极或双极开关电压进行大量介导的开关，用于从低电阻状态切换到高电阻状态，反之亦然。

    Surface Treatment to Improve Resistive-Switching Characteristics
    8.
    发明申请
    Surface Treatment to Improve Resistive-Switching Characteristics 审中-公开
    表面处理提高电阻开关特性

    公开(公告)号：US20140322887A1

    公开(公告)日：2014-10-30

    申请号：US14325015

    申请日：2014-07-07

    Applicant: Intermolecular Inc.

    Inventor： Michael Miller ,  Tony P. Chiang ,  Xiying Costa ,  Tanmay Kumar ,  Prashant B. Phatak ,  April Schricker

    IPC: H01L45/00

    CPC classification number: H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

    Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元结构的方法。 通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。 例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。 在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

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