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    Adaptive real-time power and performance optimization of multi-core processors
    2.
    发明授权
    Adaptive real-time power and performance optimization of multi-core processors 有权
    多核处理器的自适应实时功耗和性能优化

    公开(公告)号：US09189057B2

    公开(公告)日：2015-11-17

    申请号：US14041065

    申请日：2013-09-30

    Applicant: International Business Machines Corporation

    Inventor： Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

    IPC: G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/32

    Abstract: An apparatus, method, and program product for optimizing core performance and power in a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.

    Abstract translation: 一种用于在多核处理器中优化核心性能和功耗的设备，方法和程序产品。 该装置包括耦合到时钟源的多核处理器，其为一个或多个核心提供时钟频率，耦合到每个核心的独立电源，用于向每个核心提供电源电压，以及耦合到锁相环 到每个核心，用于动态调整提供给每个核心的时钟频率。 该装置还包括耦合到每个核心并被配置为收集针对每个核心测量的性能数据和功耗数据的控制器，并且使用PLL电路来调整提供给核心的电源电压，使得所述操作核心频率 核心大于为核心预设的规格核心频率，从而优化核心性能和功耗。

    ADAPTIVE REAL-TIME POWER AND PERFORMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS
    3.
    发明申请
    ADAPTIVE REAL-TIME POWER AND PERFORMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS 有权
    多核处理器的自适应实时功耗和性能优化

    公开(公告)号：US20140025972A1

    公开(公告)日：2014-01-23

    申请号：US14041065

    申请日：2013-09-30

    Applicant: International Business Machines Corporation

    Inventor： Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  James R. Moulic

    IPC: G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/32

    Abstract: An apparatus, method, and program product for optimizing core performance and power in a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.

    Abstract translation: 一种用于在多核处理器中优化核心性能和功耗的设备，方法和程序产品。 该装置包括耦合到时钟源的多核处理器，其为一个或多个核心提供时钟频率，耦合到每个核心的独立电源，用于向每个核心提供电源电压，以及耦合到锁相环 到每个核心，用于动态调整提供给每个核心的时钟频率。 该装置还包括耦合到每个核心并被配置为收集针对每个核心测量的性能数据和功耗数据的控制器，并且使用PLL电路来调整提供给核心的电源电压，使得所述操作核心频率 核心大于为核心预设的规格核心频率，从而优化核心性能和功耗。

    VIRTUALIZATION ACROSS PHYSICAL PARTITIONS OF A MULTI-CORE PROCESSOR (MCP)
    6.
    发明申请
    VIRTUALIZATION ACROSS PHYSICAL PARTITIONS OF A MULTI-CORE PROCESSOR (MCP) 有权
    多核处理器（MCP）物理分区之间的虚拟化

    公开(公告)号：US20140259013A1

    公开(公告)日：2014-09-11

    申请号：US14281062

    申请日：2014-05-19

    Applicant: International Business Machines Corporation

    Inventor： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

    IPC: G06F9/50 ,  G06F9/455

    CPC classification number: G06F9/5077 ,  G06F9/45533 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

    Abstract: Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

    Abstract translation: 除其他之外，本公开应用于具有一组（例如，一个或多个）控制/主处理元件（例如MPE）和一组子处理元件（例如SPE）的通用微处理器架构。 在这种安排下，MPEs和SPE的组织方式是使用较少数量的MPE使用体现为一组虚拟控制线程的程序代码控制一组SPE的行为。 该装置包括耦合到与核耦合的电源的MCP，以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。 根据这些特征，虚拟化控制线程可以遍历MCP的物理边界以控制不同物理分区（例如，不同于其中的物理分区）的SPE（例如，具有一个或多个SPE的逻辑分区） 虚拟化控制线程发起。

    Virtualization across physical partitions of a multi-core processor (MCP)
    7.
    发明授权
    Virtualization across physical partitions of a multi-core processor (MCP) 有权
    跨多核处理器（MCP）物理分区的虚拟化

    公开(公告)号：US09361160B2

    公开(公告)日：2016-06-07

    申请号：US14281062

    申请日：2014-05-19

    Applicant: International Business Machines Corporation

    Inventor： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

    IPC: G06F9/50 ,  G06F9/455

    CPC classification number: G06F9/5077 ,  G06F9/45533 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D10/28 ,  Y02D10/36

    Abstract: A generic microprocessor architecture is provided with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

    Abstract translation: 通用微处理器架构被提供有一组（例如，一个或多个）控制/主处理元件（例如，MPE）和一组子处理元件（例如，SPE）。 在这种安排下，MPEs和SPE的组织方式是使用较少数量的MPE使用体现为一组虚拟控制线程的程序代码控制一组SPE的行为。 该装置包括耦合到与核耦合的电源的MCP，以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。 根据这些特征，虚拟化控制线程可以遍历MCP的物理边界以控制不同物理分区（例如，不同于其中的物理分区）的SPE（例如，具有一个或多个SPE的逻辑分区） 虚拟化控制线程发起。

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