中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.017 seconds)

    Damascene integration scheme for developing metal-insulator-metal capacitors
    2.
    发明申请
    Damascene integration scheme for developing metal-insulator-metal capacitors 有权
    用于开发金属 - 绝缘体 - 金属电容器的大马士革集成方案

    公开(公告)号：US20040113235A1

    公开(公告)日：2004-06-17

    申请号：US10319724

    申请日：2002-12-13

    Applicant: International Business Machines Corporation

    Inventor： Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Kenneth J. Stein ,  Kunal Vaed ,  Richard P. Volant

    IPC: H01L029/00 ,  H01L021/20

    CPC classification number: H01L28/90 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02258 ,  H01L21/0228 ,  H01L21/31604 ,  H01L21/76807 ,  H01L21/76831 ,  H01L28/40 ,  H01L28/86

    Abstract: The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al2O3, Al2O3/Ta2O5, Al2O3/Ta2O5/Al2O3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.

    Abstract translation: 本发明涉及具有高k电介质层的独特的高表面积BEOL电容器结构及其制造方法。 这些高表面积BEOL电容器结构可用于模拟和混合信号应用。 电容器形成在具有沟槽内的基座的沟槽内，以提供额外的表面积。 顶部和底部电极使用大马士革集成方案创建。 电介质层被形成为包括例如Al 2 O 3，Al 2 O 3 / Ta 2 O 5，Al 2 O 3 / Ta 2 O 5 / Al 2 O 3等的多层电介质膜。 电介质层可以通过诸如原子层沉积或化学气相沉积的方法沉积。 电容器中使用的电介质层也可以通过金属前体的阳极氧化产生高介电常数氧化物层。

    Method of fabricating a stacked poly-poly and MOS capacitor using a sige integration scheme
    4.
    发明申请
    Method of fabricating a stacked poly-poly and MOS capacitor using a sige integration scheme 失效
    使用奇数积分方案制造堆叠多晶硅和MOS电容器的方法

    公开(公告)号：US20030092239A1

    公开(公告)日：2003-05-15

    申请号：US10292204

    申请日：2002-11-12

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Douglas D. Coolbaugh ,  James Stuart Dunn ,  Stephen Arthur St. Onge

    IPC: H01L021/8249 ,  H01L021/20

    CPC classification number: H01L28/40 ,  H01L29/94

    Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

    Abstract translation: 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器，包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层，所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层，所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。

    PREVENTION OF Ta2O5 MIM CAP SHORTING IN THE BEOL ANNEAL CYCLES
    7.
    发明申请
    PREVENTION OF Ta2O5 MIM CAP SHORTING IN THE BEOL ANNEAL CYCLES 有权
    防止Ta2O5 MIM帽在BEOL中的周期循环

    公开(公告)号：US20040104420A1

    公开(公告)日：2004-06-03

    申请号：US10249550

    申请日：2003-04-17

    Applicant: International Business Machines Corporation

    Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Joseph F. Shepard JR. ,  Kenneth J. Stein ,  Kunal Vaed

    IPC: H01L029/76

    CPC classification number: H01L28/40 ,  H01L21/31604 ,  H01L28/55

    Abstract: The present invention provides a high-performance metal-insulator-metal (MIM) capacitor which contains a high-k dielectric, yet no substantial shorting of the MIM capacitor is observed. Specifically, shorting of the MIM capacitor is substantially prevented in the present invention by forming a passivation layer between the high-k dielectric layer and each of the capacitornulls electrodes. The inventive MIM capacitor includes a first conductor; a first passivation layer located atop the first conductor; a high-k dielectric layer located atop the first passivation layer; a second passivation layer located atop the high k dielectric layer; and a second conductor located atop the second passivation layer.

    Abstract translation: 本发明提供了一种高性能金属绝缘体金属（MIM）电容器，其包含高k电介质，但没有观察到MIM电容器的实质短路。 具体地说，在本发明中通过在高k电介质层和电容器电极之间形成钝化层，实质上防止了MIM电容器的短路，本发明的MIM电容器包括：第一导体;位于顶部的第一钝化层 所述第一导体;位于所述第一钝化层顶部的高k电介质层;位于所述高k电介质层顶部的第二钝化层;以及位于所述第二钝化层顶部的第二导体。

    High performance varactor diodes
    8.
    发明申请
    High performance varactor diodes 失效
    高性能变容二极管

    公开(公告)号：US20040082124A1

    公开(公告)日：2004-04-29

    申请号：US10728140

    申请日：2003-12-04

    Applicant: International Business Machines Corporation

    Inventor： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Mohamed Youssef Hammad ,  Jeffrey B. Johnson

    IPC: H01L021/8234

    CPC classification number: H01L29/93 ,  H01L27/0808 ,  Y10S438/979

    Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

    Abstract translation: 一种变容二极管，具有在衬底中包括第一导电类型的阱区的第一电极，包括设置在所述阱区中的第二导电类型邻接隔离区的第一多个扩散区的第二电极和第二多个扩散 所述第一导电类型的区域从不邻近所述隔离区域的所述第一多个扩散区域的部分横向延伸并且具有大于所述第一多个扩散区域的掺杂剂浓度的掺杂剂浓度。 变容二极管在约0V至3V之间的施加电压范围内具有至少约3.5的可调谐性，约0V至2V之间的施加电压范围内的电容值的近似线性变化，以及至少约100的Q 大约2GHz的电路工作频率。

    Process for implanting a deep subcollector with self-aligned photo registration marks
    9.
    发明申请
    Process for implanting a deep subcollector with self-aligned photo registration marks 失效
    用于植入具有自对准照片对准标记的深子集电极的工艺

    公开(公告)号：US20020146889A1

    公开(公告)日：2002-10-10

    申请号：US09826054

    申请日：2001-04-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  John C. Malinowski

    IPC: H01L021/76 ,  H01L021/425

    CPC classification number: G03F9/708 ,  G03F9/7084 ,  H01L21/8249 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.

    Abstract translation: 提供了一种形成具有深子集电极区域和自对准对准标记的BiCMOS器件的方法。 本发明的方法包括以下步骤：（a）在形成在半导体衬底上的材料堆叠的表面上光刻地形成包括厚电介质材料的第一图案层，所述第一图案化层包括至少一个开口，并且所述半导体衬底具有 至少一个对准区域; （b）通过所述至少一个开口和所述材料堆叠执行高能/高剂量注入，以便在所述半导体衬底中形成至少一个深子集电极区域; （c）在对准区域中主要在第一图案化层的外部光刻形成第二图案化层（光致抗蚀剂或电介质）; 和（d）使用第一图案化层作为对准标记掩模，蚀刻通过材料堆叠以在下面的半导体衬底中形成对准标记。

    High performance varactor diodes
    10.
    发明申请
    High performance varactor diodes 失效

    公开(公告)号：US20040032004A1

    公开(公告)日：2004-02-19

    申请号：US10064754

    申请日：2002-08-14

    Applicant: International Business Machines Corporation

    Inventor： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Mohamed Youssef Hammad ,  Jeffrey B. Johnson

    IPC: H01L029/00 ,  H01L021/8238

    CPC classification number: H01L29/93 ,  H01L27/0808 ,  Y10S438/979

    Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Patent Agency Ranking