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公开(公告)号：US09496018B2
公开(公告)日：2016-11-15
申请号：US14676292
申请日：2015-04-01
发明人： John K. Debrosse , Blake G. Fitch , Michele M. Franceschini , Todd E. Takken , Daniel C. Worledge
IPC分类号： G11C11/16
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
摘要翻译： 存储器包括非易失性存储器件，每个存储器件具有多个非易失性存储器单元。 写控制器使用具有写总线驱动器，接收器和写总线拓扑的写数据通道以N组的方式将比特流分组到存储器件，其利用高速信令优化对存储器件的写入速度。 连续的比特组被写入相应的存储器件中的连续的存储器单元。 自参考读取控制器使用具有读驱动器，接收器和读总线拓扑的读通道从存储器件读取位，其中不包括高速或低延迟数据传输的设计要求。
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公开(公告)号：US09569109B2
公开(公告)日：2017-02-14
申请号：US14747976
申请日：2015-06-23
发明人： John K. Debrosse , Blake G. Fitch , Michele M. Franceschini , Todd E. Takken , Daniel C. Worledge
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
摘要翻译： 存储器包括非易失性存储器件，每个存储器件具有多个非易失性存储器单元。 写控制器使用具有写总线驱动器，接收器和写总线拓扑的写数据通道以N组的方式将比特流分组到存储器件，其利用高速信令优化对存储器件的写入速度。 连续的比特组被写入相应的存储器件中的连续的存储器单元。 自参考读取控制器使用具有读驱动器，接收器和读总线拓扑的读通道从存储器件读取位，其中不包括高速或低延迟数据传输的设计要求。
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公开(公告)号：US09536926B1
公开(公告)日：2017-01-03
申请号：US14978013
申请日：2015-12-22
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/165 , H01L23/5252 , H01L27/228 , H01L43/02 , H01L43/08
摘要： Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junction serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage.
摘要翻译： 通过将第一场效应晶体管和第二场效应晶体管与所述第一场效应晶体管和第二场效应晶体管串联连接所述磁隧道结，从而防止由非选择的磁隧道结反熔丝的栅极编程电压降引起的磁隧道结反熔丝器件， 栅极连接到正电源电压，而第二场效应晶体管的栅极可切换地连接到编程电压。
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公开(公告)号：US09792052B2
公开(公告)日：2017-10-17
申请号：US15272933
申请日：2016-09-22
发明人： John K. Debrosse , Blake G. Fitch , Michele M. Franceschini , Todd E. Takken , Daniel C. Worledge
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.
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