公开(公告)号：US20030230549A1

公开(公告)日：2003-12-18

申请号：US10170914

申请日：2002-06-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Douglas A. Buchanan ,  Eduard A. Cartier ,  Evgeni Gousev ,  Harald Okorn-Schmidt ,  Katherine L. Saenger

IPC: C23F001/00 ,  B44C001/22 ,  C03C015/00 ,  C03C025/68

CPC classification number: H01L21/31122 ,  Y10S438/924

Abstract: A system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an energetic particle bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. Besides using the ion implantation damage (I/I damage) plus wet etch technique to metal oxides (including metal oxides not previously etchable by wet methods), other damage methods including lower energy, plasma-based ion bombardment, may be implemented. Plasma-based ion bombardment typically uses simpler and cheaper tooling, and results in less collateral damage to underlying structures as the damage profile can be more easily localized to the depth of the thin metal oxide film.

Abstract translation: 一种在半导体结构中图案化金属氧化物材料的系统和方法。 该方法包括在衬底上沉积金属氧化物材料层的第一步骤。 然后，在金属氧化物层之上形成图案化掩模层，留下暴露金属氧化物层的一个或多个第一区域。 接着对金属氧化物层的暴露的第一区域进行高能粒子轰击处理，从而破坏金属氧化物层的第一区域。 然后通过化学蚀刻去除金属氧化物层的暴露和损坏的第一区域。 有利地，该系统和方法被实现以在小规模半导体器件中提供高k电介质材料。 除了使用离子注入损伤（I / I损伤）以及湿法蚀刻技术对金属氧化物（包括以前不能用湿法蚀刻的金属氧化物）外，还可以实施包括较低能量，基于等离子体的离子轰击等其他损伤方法。 基于等离子体的离子轰击通常使用更简单和更便宜的工具，并且导致对下面的结构的较少的附带损伤，因为损伤分布可以更容易地定位于薄金属氧化物膜的深度。

公开(公告)号：US20030098618A1

公开(公告)日：2003-05-29

申请号：US09996148

申请日：2001-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David R. Greenberg ,  Hariklia Deligianni ,  Robert A. Groves ,  Christopher V. Jahnes ,  Jennifer L. Lund ,  Katherine L. Saenger ,  Richard P. Volant

IPC: H02H001/00

CPC classification number: B81B3/0016 ,  B81C2201/112 ,  H01H1/24 ,  H01H59/0009 ,  H01H2001/0089 ,  Y10T307/826 ,  Y10T307/911 ,  Y10T307/937

Abstract: A micro-electro mechanical switch having a restoring force sufficiently large to overcome stiction is described. The switch is provided with a deflectable conductive beam and multiple electrodes coated with an elastically deformable conductive layer. A restoring force which is initially generated by a single spring constant k0 upon the application of a control voltage between the deflectable beam and a control electrode coplanar to the contact electrodes is supplemented by adding to k0 additional spring constants k1, . . . , kn provided by the deformable layers, once the switch nears closure and the layers compress. In another embodiment, deformable, spring-like elements are used in lieu of the deformable layers. In an additional embodiment, the compressible layers or deformable spring-like elements are affixed to the deflecting beam facing the switch electrodes

Abstract translation: 描述了具有足够大以克服静止的恢复力的微电机械开关。 开关设置有可偏转的导电束和涂覆有可弹性变形的导电层的多个电极。 在施加可调光束和与接触电极共面的控制电极之间的控制电压时，最初由单个弹簧常数k0产生的恢复力通过增加k0个额外的弹簧常数k1来补充。 。 。 由可变形层提供的，一旦开关接近闭合并且层压缩。 在另一个实施例中，使用可变形的弹簧状元件代替可变形层。 在另外的实施例中，可压缩层或可变形的弹簧状元件固定到面向开关电极的偏转梁

公开(公告)号：US20020096717A1

公开(公告)日：2002-07-25

申请号：US09769170

申请日：2001-01-25

Applicant: International Business Machines Corporation

Inventor： Jack Oon Chu ,  Alfred Grill ,  Dean A. Herman JR. ,  Katherine L. Saenger

IPC: H01L021/00 ,  H01L021/84 ,  H01L027/01 ,  H01L023/48 ,  H01L029/40

CPC classification number: H01L27/1203 ,  H01L21/76259

Abstract: A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a nulltransferablenull device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least one porous silicon germanium alloy layer alone or in combination with at least one porous Si layer. Also described is an integrated circuit comprising the transfered device layer described above.

Abstract translation: 一种用于在绝缘基板上形成集成电路的方法，其特征在于包括以下步骤：在含有至少部分结晶的多孔剥离层的种晶片基板上形成半导体层，处理该半导体层以形成“可转移”器件层， 至少一个半导体器件，并且在将所述器件层与种子晶片衬底分离之前或之后将所述可转移器件层结合到最终的绝缘衬底。 描述了用于从种子晶片衬底分离半导体层的第二种方法，其中初始连接半导体层和晶种晶片衬底的至少部分结晶的多孔层通过以下步骤被分裂或分开：（i）引入包括 水进入所述多孔层的孔中，和（ii）通过凝固或冷冻来膨胀所述流体以分离多孔层。 所述至少部分结晶的多孔层可以单独地或与至少一个多孔Si层组合地并入至少一个多孔硅锗合金层。 还描述了包括上述转移器件层的集成电路。

公开(公告)号：US20040198026A1

公开(公告)日：2004-10-07

申请号：US10826712

申请日：2004-04-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jack Oon Chu ,  Alfred Grill ,  Dean A. Herman JR. ,  Katherine L. Saenger

IPC: H01L027/10 ,  H01L021/301 ,  H01L021/46 ,  H01L021/78 ,  H01L021/20 ,  H01L021/36

CPC classification number: H01L27/1203 ,  H01L21/76259

Abstract: A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a nulltransferablenull device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least one porous silicon germanium alloy layer alone or in combination with at least one porous Si layer. Also described is an integrated circuit comprising the transfered device layer described above.

Abstract translation: 一种用于在绝缘基板上形成集成电路的方法，其特征在于包括以下步骤：在含有至少部分结晶的多孔剥离层的种晶片基板上形成半导体层，处理该半导体层以形成“可转移”器件层， 至少一个半导体器件，并且在将所述器件层与种子晶片衬底分离之前或之后将所述可转移器件层结合到最终的绝缘衬底。 描述了用于从种子晶片衬底分离半导体层的第二种方法，其中初始连接半导体层和晶种晶片衬底的至少部分结晶的多孔层通过以下步骤被分裂或分开：（i）引入包括 水进入所述多孔层的孔中，和（ii）通过凝固或冷冻来膨胀所述流体以分离多孔层。 所述至少部分结晶的多孔层可以单独地或与至少一个多孔Si层组合地并入至少一个多孔硅锗合金层。 还描述了包括上述转移器件层的集成电路。

公开(公告)号：US20040127001A1

公开(公告)日：2004-07-01

申请号：US10331038

申请日：2002-12-27

Applicant: International Business Machines Corporation

Inventor： Matthew E. Colburn ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Katherine L. Saenger

IPC: H01L021/3205

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectric through a perforated bridge layer that connects the top surfaces of the interconnects laterally; performing multilevel extraction of a sacrificial layer; sealing the bridge in a controlled manner; and decreasing the effective dielectric constant of a membrane by perforating it using sub-optical lithography patterning techniques.

Abstract translation: 用于在衬底上制造低k和超低k多层互连结构的方法包括：一组通过气隙横向分离的互连; 在仅在金属线下面的双镶嵌结构的通孔层中形成支撑层; 通过横向连接互连的顶表面的穿孔桥接层去除牺牲电介质; 执行牺牲层的多级提取; 以受控的方式密封桥梁; 并通过使用亚光学光刻图案化技术对膜进行穿孔来降低膜的有效介电常数。

公开(公告)号：US20040113279A1

公开(公告)日：2004-06-17

申请号：US10319967

申请日：2002-12-16

Applicant: International Business Machines Corporation

Inventor： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P.E. Smith ,  Wei-tsu Tseng

IPC: H01L023/48 ,  H01L023/52 ,  H01L021/4763

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

Abstract translation: 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。