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1.发明申请公开(公告)号：US20040051162A1
公开(公告)日：2004-03-18
申请号：US10243540
申请日：2002-09-13
IPC分类号： H01L029/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： As disclosed herein, a structure and method is provided for forming an integrated circuit including a reduced programming voltage antifuse on a semiconductor substrate. The method includes doping a portion of a semiconductor substrate with nitrogen and a charge carrier dopant source, and forming a thin dielectric over the doped portion of the semiconductor substrate, wherein the thin dielectric is subject to breakdown upon application of a breakdown voltage. The method further includes forming a first conductor separated from the semiconductor substrate by the thin dielectric, and forming a second conductor conductively coupled to the doped portion of the semiconductor substrate.
摘要翻译： 如本文所公开的，提供了一种用于在半导体衬底上形成包括减少的编程电压反熔丝的集成电路的结构和方法。 该方法包括用氮和电荷载体掺杂剂源掺杂半导体衬底的一部分，以及在半导体衬底的掺杂部分上形成薄的电介质，其中薄的电介质在施加击穿电压时被击穿。 该方法还包括通过薄电介质形成与半导体衬底分离的第一导体，以及形成与半导体衬底的掺杂部分导电耦合的第二导体。
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2.发明申请公开(公告)号：US20040166624A1
公开(公告)日：2004-08-26
申请号：US10248819
申请日：2003-02-21
IPC分类号： H01L021/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814
摘要： The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.
摘要翻译： CMOS电路的速度通过在NFET上施加纵向拉伸应力和PFET上的纵向压缩应力，通过将元素周期表第八列中的NFET离子的源和漏极注入氢中并将其植入到 来自周期表第四和第六列的PFET离子的源极和漏极。
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3.发明申请Structure and method of vertical transistor DRAM cell having a low leakage buried strap 失效具有低泄漏掩埋带的垂直晶体管DRAM单元的结构和方法公开(公告)号：US20040066666A1
公开(公告)日：2004-04-08
申请号：US10265558
申请日：2002-10-04
IPC分类号： G11C011/24
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.
摘要翻译： 本文公开了一种用于垂直晶体管DRAM单元的结构和方法，该垂直晶体管DRAM单元具有将沟槽下部的存储电容器导电连接到其上方的垂直晶体管的低泄漏掩埋带外扩散。 在所公开的结构和方法中，掩埋带外扩散（BSOD）沿着具有减小的厚度的隔离环的一部分延伸，否则减小的厚度小于隔离环的厚度。 在特定实施例中，形成自对准的轻掺杂漏极（LDD）延伸，在LDD之上的BSOD和垂直晶体管之间延伸。
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4.发明申请HIGH PERFORMANCE LOGIC AND HIGH DENSITY EMBEDDED DRAM WITH BORDERLESS CONTACT AND ANTISPACER 失效高性能逻辑和高密度嵌入式DRAM与无边界接触和防抖公开(公告)号：US20030224573A1
公开(公告)日：2003-12-04
申请号：US10160540
申请日：2002-05-31
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
IPC分类号： H01L029/76
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit such as a memory chip with embedded logic or a logic array or processor with imbedded large cache memory in which all significant sources of incompatibility between array transistors and high performance logic transistors are resolved. The integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, F, and memory cell areas or 8-12 F2 and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel length of 0.7F or less, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译： 诸如具有嵌入式逻辑的存储器芯片或具有嵌入式大型高速缓冲存储器的逻辑阵列或处理器的集成电路，其中解决了阵列晶体管和高性能逻辑晶体管之间的所有重要的不兼容的源。 集成电路包括具有由最小光刻特征尺寸F和存储单元面积分离的阵列晶体管的存储单元，以及由扩散阻挡层封装的8-12F 2和未硅化的金属位线，而高性能逻辑晶体管可形成在 相同的芯片不损害性能，包括0.7F或更小的有效沟道长度，用于低源极/漏极接触电阻的硅化触点，用于控制短沟道效应的延伸和晕轮注入以及具有高杂质浓度的双功函数半导体栅极，以及 相应地薄的耗尽层厚度与现有技术的栅介质厚度相当。 该结构通过使用掩模或抗间隔物（优选易于平坦化的材料）开发不同材料的厚/高结构来实现，并且使用平坦化为不同材料的结构的高度的类似掩模以使基板和栅极注入分离 在逻辑晶体管中。
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公开(公告)号：US20030168687A1
公开(公告)日：2003-09-11
申请号：US10096219
申请日：2002-03-11
IPC分类号： H01L027/108
CPC分类号： H01L27/10864 , H01L21/26586 , H01L27/10838 , H01L29/66666 , H01L29/7827
摘要： Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implantsnullan angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.
摘要翻译： 在垂直MOSFET晶体管中的体效应显着降低，并且在具有在栅极处具有峰值的阈值注入的垂直晶体管中的其它器件参数不受影响，并且注入浓度分布从栅极快速下降到具有低p阱的平台 浓度值。 优选实施例采用两个体植入物 - 成角度的植入物，其在浇口处具有设置Vt的峰值，以及设置阱掺杂剂浓度的横向均匀的低剂量注入。
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公开(公告)号：US20030013259A1
公开(公告)日：2003-01-16
申请号：US09904612
申请日：2001-07-13
IPC分类号： H01L021/8242 , H01L021/20
CPC分类号： H01L27/10867
摘要： A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.
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公开(公告)号：US20040113174A1
公开(公告)日：2004-06-17
申请号：US10318600
申请日：2002-12-12
IPC分类号： H01L031/109
CPC分类号： H01L29/7846 , H01L21/76232 , H01L21/823807 , H01L21/823878 , H01L29/785
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.
摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择适当的STI填充材料将张力和/或压缩施加在基底上。 STI区域形成在衬底层中并且在相邻衬底区域上施加力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，实现了IC性能的提高。
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公开(公告)号：US20030155609A1
公开(公告)日：2003-08-21
申请号：US10341831
申请日：2003-01-14
IPC分类号： H01L029/76
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.
摘要翻译： 6F2存储单元结构及其制造方法。 存储单元结构包括位于含Si衬底中的以行和列排列的多个存储单元。 每个存储单元包括具有暴露的栅极导体区域和形成在MOSFET的相对侧壁上的两个栅极的双门控垂直MOSFET。 存储单元结构还包括覆盖双门控垂直MOSFET并与暴露的栅极导体区域接触的多个字线以及与字线正交的多个位线。 沟槽隔离区位于与存储单元行相邻的位置。 存储单元结构还包括位于含硅衬底中并与字线和位线自对准的多个穿通停止区域。 穿通停止区域的一部分在位线之下彼此重叠，并且每个区域用于将相邻的掩埋区域彼此电隔离。
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公开(公告)号：US20040262784A1
公开(公告)日：2004-12-30
申请号：US10604190
申请日：2003-06-30
IPC分类号： H01L027/088
CPC分类号： H01L29/7842 , H01L21/823864 , H01L29/7843 , Y10S257/90 , Y10S438/938
摘要： A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.
摘要翻译： 半导体器件结构包括形成在同一衬底上的至少两个场效应晶体管，第一场效应晶体管包括具有第一宽度的间隔物，第二场效应晶体管包括具有第二宽度的压缩间隔物，第一宽度不同于所述第一宽度 第二宽度。 优选地，第一宽度比第二宽度窄。 拉伸应力介电膜在晶体管上形成阻挡蚀刻停止层。
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公开(公告)号：US20040203208A1
公开(公告)日：2004-10-14
申请号：US10838018
申请日：2004-05-03
IPC分类号： H01L021/336
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.
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