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    High-breakdown-voltage resistance element for integrated circuit with a plurality of multilayer, overlapping electrodes
    2.
    发明授权
    High-breakdown-voltage resistance element for integrated circuit with a plurality of multilayer, overlapping electrodes 失效
    具有多个多层重叠电极的集成电路的高耐击穿电压元件

    公开(公告)号：US4423433A

    公开(公告)日：1983-12-27

    申请号：US156015

    申请日：1980-06-03

    申请人： Ichiro Imaizumi ,  Shikayuki Ochi ,  Masatoshi Kimura ,  Masayoshi Yoshimura ,  Takashi Yamaguchi ,  Toyomasa Koda

    发明人： Ichiro Imaizumi ,  Shikayuki Ochi ,  Masatoshi Kimura ,  Masayoshi Yoshimura ,  Takashi Yamaguchi ,  Toyomasa Koda

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L29/41 ,  H01L29/8605 ,  H01L27/02

    CPC分类号： H01L29/8605

    摘要： A high-breakdown-voltage resistance element comprises a semiconductor body, an impurity layer disposed in a surface region of the semiconductor body to provide a resistor body, a first electrode connected to one end of the resistor body through a contact hole in a first insulating film formed on the surface of the semiconductor body, and a second electrode connected to the other end of the resistor body through another contact hole in the insulating film. A second insulating film is formed on the first and second electrodes, and a third electrode is connected to the first electrode through a contact hole in the second insulating film, so that the entire surface of the resistor body and adjacent areas are covered with the first, second and third electrodes.

    摘要翻译： 高耐压电阻元件包括半导体本体，设置在半导体本体的表面区域中以提供电阻体的杂质层，通过第一绝缘体中的接触孔与电阻体的一端连接的第一电极 形成在半导体本体的表面上的膜，以及通过绝缘膜中的另一接触孔与电阻体的另一端连接的第二电极。 第二绝缘膜形成在第一和第二电极上，第三电极通过第二绝缘膜中的接触孔连接到第一电极，使得电阻体和相邻区域的整个表面被第一电极 ，第二和第三电极。

    Insulated gate field effect transistor with source field shield extending over multiple region channel
    3.
    发明授权
    Insulated gate field effect transistor with source field shield extending over multiple region channel 失效
    绝缘栅场效应晶体管，源场屏蔽延伸到多个区域通道

    公开(公告)号：US4172260A

    公开(公告)日：1979-10-23

    申请号：US853548

    申请日：1977-11-21

    申请人： Takeaki Okabe ,  Isao Yoshida ,  Shikayuki Ochi ,  Hidefumi Itoh ,  Masatomo Furumi ,  Toru Toyabe ,  Mineo Katsueda ,  Yukio Shirota

    发明人： Takeaki Okabe ,  Isao Yoshida ,  Shikayuki Ochi ,  Hidefumi Itoh ,  Masatomo Furumi ,  Toru Toyabe ,  Mineo Katsueda ,  Yukio Shirota

    IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/73 ,  H01L29/78

    CPC分类号： H01L29/404 ,  H01L29/7835

    摘要： In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.

    摘要翻译： 在绝缘栅场效应晶体管中，具有P导电类型的源区和漏区，它们以相互间隔开的方式设置在N-导电类型的半导体衬底的表面部分中，栅极 电极通过源极区域和漏极区域之间的衬底上的绝缘膜设置，绝缘栅极场效应晶体管，其中所述漏极区域与所述栅电极隔开，中间区域和高电阻区域的两个区域是 的P导电类型并且从所述漏极区域朝向所述栅电极的侧面依次延伸设置在位于所述漏极区域和所述栅电极之间的衬底的表面部分中，所述中间区域的杂质浓度低于 所述漏极区，所述高电阻区的杂质浓度低于所述中间区的杂质浓度 并且源电极通过所述绝缘膜延伸超过所述栅电极和所述高电阻区域，并且终止于所述中间区域上。

    Insulated-gate semiconductor device
    4.
    发明授权
    Insulated-gate semiconductor device 失效
    绝缘栅半导体器件

    公开(公告)号：US4213140A

    公开(公告)日：1980-07-15

    申请号：US922371

    申请日：1978-07-06

    申请人： Takeaki Okabe ,  Isao Yoshida ,  Mineo Katsueda ,  Hidefumi Ito ,  Masatomo Furumi ,  Shikayuki Ochi

    发明人： Takeaki Okabe ,  Isao Yoshida ,  Mineo Katsueda ,  Hidefumi Ito ,  Masatomo Furumi ,  Shikayuki Ochi

    IPC分类号： H03F1/52 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H03F1/42

    CPC分类号： H01L27/0251

    摘要： An insulated-gate semiconductor device wherein a first region is formed in the surface of a semiconductor substrate, the first region having a conductivity type opposite to that of the substrate, two insulated-gate FET's are formed within the first region, the drain of the first insulated-gate FET and that of the second insulated-gate FET are made common, the drains are electrically connected to the first region, and the gate of the first insulated-gate FET and the source of the second insulated-gate FET, and the gate of the second insulated-gate FET and the source of the first insulated-gate FET are respectively connected, thereby to prevent the occurrence of a negative resistance.

    摘要翻译： 一种绝缘栅半导体器件，其中第一区域形成在半导体衬底的表面中，所述第一区域具有与衬底的导电类型相反的导电类型，在所述第一区域内形成有两个绝缘栅FET， 第一绝缘栅极FET和第二绝缘栅极FET的漏极共同，漏极电连接到第一区域，第一绝缘栅极FET的栅极和第二绝缘栅极FET的源极，以及 第二绝缘栅FET的栅极和第一绝缘栅FET的源极分别连接，从而防止产生负电阻。

    High-voltage circuit for insulated gate field-effect transistor
    6.
    发明授权
    High-voltage circuit for insulated gate field-effect transistor 失效
    绝缘栅场效应晶体管高压电路

    公开(公告)号：US4317055A

    公开(公告)日：1982-02-23

    申请号：US36972

    申请日：1979-05-08

    申请人： Isao Yoshida ,  Minoru Nagata ,  Shikayuki Ochi ,  Hisao Katto

    发明人： Isao Yoshida ,  Minoru Nagata ,  Shikayuki Ochi ,  Hisao Katto

    IPC分类号： H03F3/345 ,  H03F1/22 ,  H03F3/34 ,  H03F3/42 ,  H03K3/353 ,  H01L29/78 ,  H03F3/16 ,  H03K17/687

    CPC分类号： H03K17/567 ,  H03F1/22 ,  H03F1/223 ,  H03F3/42 ,  H03F3/423 ,  H01L2924/0002

    摘要： A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.

    摘要翻译： 提供了一种用于绝缘栅场效应晶体管（MOSFET）的高电压电路，其中两个MOSFET串联连接，第一MOSFET的源极和栅极分别用作高压电路的源极端子和栅极端子， 第二MOSFET的漏极用作电路的漏极端子。 第一和第二电阻器串联在源极端子和漏极端子之间，偏置电压源连接在两个电阻器和第二个MOSFET的栅极之间。 由于这些连接，由于在使第二MOSFET处于“导通”状态时偏置电压效应的影响，高压电路的“导通”电阻得到改善。