公开(公告)号：US20250053719A1

公开(公告)日：2025-02-13

申请号：US18932446

申请日：2024-10-30

Applicant: IMEC vzw

Inventor： Subrat Mishra ,  Pieter Weckx ,  Alessio Spessot ,  Francky Catthoor

IPC: G06F30/3308 ,  G06F30/392 ,  G06F30/398 ,  G06F115/06 ,  G06F119/04

Abstract: A system and method of simulating device aging based on a digital waveform representative of a workload of an electronic device are disclosed. In one aspect, the method comprises grouping contiguous sets of cycles into segments, each set corresponding to a segment. Each segment has values for a combination of segment parameters that are unique from each of the other segments and a start point that is separated from a start point of an adjacent segment by a pre-defined distance criterion. Grouping the sets into the segments comprises, for each segment: sampling one or more sequential cycles of the workload, generating the segment based on the sampled contiguous cycles having a period exceeding a threshold period, and determining the values for the combination of segment parameters. The method further comprises applying an aging model to the segments to simulate the aging. The segments are a representation of the digital waveform.

公开(公告)号：US11462443B2

公开(公告)日：2022-10-04

申请号：US17110604

申请日：2020-12-03

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

公开(公告)号：US20210183711A1

公开(公告)日：2021-06-17

申请号：US17110604

申请日：2020-12-03

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

公开(公告)号：US20190205095A1

公开(公告)日：2019-07-04

申请号：US16222767

申请日：2018-12-17

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Mohit Gupta ,  Wim Dehaene ,  Sushil Sakhare ,  Pieter Weckx

IPC: G06F7/523 ,  G11C11/412 ,  G11C11/419 ,  G06N3/063 ,  G06N3/04

CPC classification number: G06F7/5443 ,  G06F7/607 ,  G06F2207/4824 ,  G06N3/063 ,  H03K19/215

Abstract: A semiconductor cell comprising a memory element for storing a first binary operand is disclosed. In one aspect, the memory element provides complementary memory outputs, and a multiplication block that is locally and uniquely associated with the memory element. The multiplication block may be configured to receive complementary input signals representing binary input data and the complementary memory outputs of the associated memory element representing the first binary operand, implement a multiplication operation on these signals, and provide an output of the multiplication operation to an output port. An array of semiconductor cells and a neural network circuit comprising such array are also disclosed.

公开(公告)号：US20180174642A1

公开(公告)日：2018-06-21

申请号：US15851531

申请日：2017-12-21

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/408 ,  H01L29/08 ,  H01L29/423

CPC classification number: G11C11/412 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: The disclosed technology generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) device. One aspect of the disclosed technology is a bit cell for a static random access memory (SRAM) comprising: a first and a second vertical stack of transistors arranged on a substrate. Each stack includes a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a horizontally extending channel, the pull-up transistor and the pull-down transistor having a common gate electrode extending vertically between the pull-up transistor and the pull-down transistor and the pass transistor having a gate electrode being separate from the common gate electrode. A source/drain of the pull-up transistor and of the pull-down transistor of the first stack, a source/drain of the pass transistor of the first stack and the common gate electrode of the pull-up and pull-down transistors of the second stack are electrically interconnected. A source/drain of the pull-up transistor and of the pull-down transistor of the second stack, a source/drain of the pass transistor of the second stack and the common gate electrode of the pull-up and pull-down transistors of the first stack are electrically interconnected.

公开(公告)号：US11704462B2

公开(公告)日：2023-07-18

申请号：US16522555

申请日：2019-07-25

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Pieter Weckx ,  Dimitrios Rodopoulos ,  Benjamin Kaczer ,  Francky Catthoor

IPC: G06F30/367

CPC classification number: G06F30/367

Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

公开(公告)号：US20220100939A1

公开(公告)日：2022-03-31

申请号：US17039571

申请日：2020-09-30

Applicant: IMEC vzw

Inventor： Subrat Mishra ,  Pieter Weckx ,  Francky Catthoor ,  Alessio Spessot

IPC: G06F30/3308 ,  G06F30/392

Abstract: A system and method of simulating device aging based on a digital waveform representative of a workload of an electronic device are disclosed. In one aspect, the method comprises grouping contiguous sets of cycles into segments, each set corresponding to a segment. Each segment has values for a combination of segment parameters that are unique from each of the other segments and a start point that is separated from a start point of an adjacent segment by a pre-defined distance criterion. Grouping the sets into the segments comprises, for each segment: sampling one or more sequential cycles of the workload, generating the segment based on the sampled contiguous cycles having a period exceeding a threshold period, and determining the values for the combination of segment parameters. The method further comprises applying an aging model to the segments to simulate the aging. The segments are a representation of the digital waveform.

公开(公告)号：US20200089829A1

公开(公告)日：2020-03-19

申请号：US16522555

申请日：2019-07-25

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Pieter Weckx ,  Dmitrios Rodopoulos ,  Benjamin Kaczer ,  Francky Catthoor

IPC: G06F17/50

Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

公开(公告)号：US20220108948A1

公开(公告)日：2022-04-07

申请号：US17494087

申请日：2021-10-05

Applicant: Imec vzw

Inventor： Pieter Weckx

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: A method includes: producing on a substrate a stack of: a first layer including a first dielectric material, a second layer including dielectric material on the first layer, and an etch stop layer between the first layer and the second layer, etching a trench through the second layer, the etch stop layer, and the first layer, producing a lower conductive line in the trench, producing a third layer including a second dielectric material in the trench and on the tower conductive line, removing a first portion of the second layer, such that a second portion of the second layer remains in contact with the etch stop layer, etching a via opening through the third layer in the trench, using the second portion of the second layer as a mask, and depositing a conductive upper line and an interconnect via on the lower conductive line within the via opening.

公开(公告)号：US11244949B2

公开(公告)日：2022-02-08

申请号：US16441725

申请日：2019-06-14

Applicant: IMEC vzw

Inventor： Pieter Weckx ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L29/76 ,  H01L27/11 ,  G11C5/02 ,  G11C5/06 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8238

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.