公开(公告)号：US20180308804A1

公开(公告)日：2018-10-25

申请号：US16025338

申请日：2018-07-02

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Kok Yau Chua ,  Swee Kah Lee ,  Chee Yang NG ,  Valentyn Solomko

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6677 ,  H01L2224/48227 ,  H01L2924/3025

Abstract: A device includes a substrate that includes conductive structures and has a first surface that is opposite to a second surface. Conductive pillars are built up over and electrically coupled to at least one of the conductive structures. An integrated circuit is disposed over the first surface and electrically coupled to the conductive structures. A molding compound is formed over the first surface of the substrate.

公开(公告)号：US20230027669A1

公开(公告)日：2023-01-26

申请号：US17872338

申请日：2022-07-25

Applicant: Infineon Technologies AG

Inventor： Chee Yang NG ,  Edmund RIEDL ,  Joseph Victor SOOSAI PRAKASAM

IPC: H01L23/00 ,  H01L23/495

Abstract: An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.

公开(公告)号：US20220122906A1

公开(公告)日：2022-04-21

申请号：US17485742

申请日：2021-09-27

Applicant: Infineon Technologies AG

Inventor： Sergey YUFEREV ,  Paul Armand Asentista CALO ,  Theng Chao LONG ,  Josef MAERZ ,  Chee Yang NG ,  Petteri PALM ,  Wae Chet YONG

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/00

Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

公开(公告)号：US20230335516A1

公开(公告)日：2023-10-19

申请号：US18125252

申请日：2023-03-23

Applicant: Infineon Technologies AG

Inventor： Chee Yang NG ,  Chew Yeek LAU ,  Swee Kah LEE ,  Joseph Victor SOOSAI PRAKASAM ,  Hui Khin TAN

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/03 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/11 ,  H01L21/56 ,  H01L23/49838 ,  H01L24/13 ,  H01L2924/141 ,  H01L2224/16225 ,  H01L2924/182

Abstract: A method of manufacturing a package is disclosed. In one example, the method comprises applying a metallic connection structure, which comprises a solder or sinter material, on a sacrificial carrier. An electronic component is mounted on the metallic connection structure. At least part of the electronic component and of the metallic connection structure is encapsulated. Thereafter, the sacrificial carrier is removed to thereby expose at least part of the metallic connection structure.

公开(公告)号：US20180108616A1

公开(公告)日：2018-04-19

申请号：US15297744

申请日：2016-10-19

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Kok Yau Chua ,  Swee Kah Lee ,  Chee Yang NG ,  Valentyn Solomko

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6677 ,  H01L2224/48227 ,  H01L2924/3025

Abstract: A device includes a substrate that includes conductive structures and has a first surface that is opposite to a second surface. Conductive pillars are built up over and electrically coupled to at least one of the conductive structures. An integrated circuit is disposed over the first surface and electrically coupled to the conductive structures. A molding compound is formed over the first surface of the substrate.

公开(公告)号：US20240274563A1

公开(公告)日：2024-08-15

申请号：US18415880

申请日：2024-01-18

Applicant: Infineon Technologies AG

Inventor： Hock Heng CHONG ,  Hui Khin TAN ,  Chee Yang NG ,  Swee Kah LEE

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/40 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/16227 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/81815 ,  H01L2224/84815 ,  H01L2924/014 ,  H01L2924/0536 ,  H01L2924/0541 ,  H01L2924/0543 ,  H01L2924/0544 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108

Abstract: A solder structure and method is disclosed. In one example, the solder structure includes a solder material, and a coating which at least partially coats the solder material and is configured for protecting the solder material against solder spreading. The coating is at least partially disrupted when establishing a solder connection between the solder material and a solderable structure.