公开(公告)号：US20160043050A1

公开(公告)日：2016-02-11

申请号：US14821705

申请日：2015-08-08

Applicant: Infineon Technologies AG

Inventor： Swee Kah LEE

IPC: H01L23/00 ,  B32B15/01 ,  H01L23/495

CPC classification number: H01L24/14 ,  B32B15/01 ,  B32B15/018 ,  H01L23/488 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L2224/1146 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/48247 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81469 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85469 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/0105 ,  H01L2924/00012

Abstract: A metallization stack for a chip arrangement is provided, wherein the metallization stack comprises a first metallic layer; a plating layer comprising an alloy comprising nickel and zinc arranged over the first metallic structure; and a second metallic layer arranged over the plating layer.

Abstract translation: 提供了一种用于芯片布置的金属化堆叠，其中金属化堆叠包括第一金属层; 镀层，其包含布置在所述第一金属结构上方的包含镍和锌的合金; 以及布置在镀层上的第二金属层。

公开(公告)号：US20240006260A1

公开(公告)日：2024-01-04

申请号：US18144578

申请日：2023-05-08

Applicant: Infineon Technologies AG

Inventor： Chee Hong LEE ,  Soon Lock GOH ,  Chai Chee LEE ,  Swee Kah LEE ,  Luay Kuan ONG ,  Chee Voon TAN

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L21/565 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49562

Abstract: A package is disclosed. In one example, the package includes an electronic component and an encapsulant encapsulating at least part of the electronic component. A first electrically conductive structure is arranged on one side of the electronic component, a second electrically conductive structure arranged on an opposing other side of the electronic component and being electrically coupled with the electronic component, and at least one sidewall recess at the encapsulant. The first electrically conductive structure and the second electrically conductive structure are configured to be at different electric potentials during operation of the package. The first electrically conductive structure and the second electrically conductive structure are exposed at opposing main surfaces of the encapsulant.

公开(公告)号：US20240274563A1

公开(公告)日：2024-08-15

申请号：US18415880

申请日：2024-01-18

Applicant: Infineon Technologies AG

Inventor： Hock Heng CHONG ,  Hui Khin TAN ,  Chee Yang NG ,  Swee Kah LEE

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/40 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/16227 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/81815 ,  H01L2224/84815 ,  H01L2924/014 ,  H01L2924/0536 ,  H01L2924/0541 ,  H01L2924/0543 ,  H01L2924/0544 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108

Abstract: A solder structure and method is disclosed. In one example, the solder structure includes a solder material, and a coating which at least partially coats the solder material and is configured for protecting the solder material against solder spreading. The coating is at least partially disrupted when establishing a solder connection between the solder material and a solderable structure.

公开(公告)号：US20240186152A1

公开(公告)日：2024-06-06

申请号：US18388581

申请日：2023-11-10

Applicant: Infineon Technologies AG

Inventor： Roslie Saini BAKAR ,  Hock Heng CHONG ,  Swee Kah LEE ,  Wei Wei YONG

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3185

Abstract: A method of processing chips is disclosed. In one example, the method comprises encapsulating mutually spaced chips by an encapsulant comprising a locally curable material. The encapsulated chips with the encapsulant are separated into a plurality of encapsulated chip sections by locally curing selectively portions of the encapsulant covering at least a portion of the chips without curing other portions of the encapsulant apart from the encapsulated chip sections.

公开(公告)号：US20230335516A1

公开(公告)日：2023-10-19

申请号：US18125252

申请日：2023-03-23

Applicant: Infineon Technologies AG

Inventor： Chee Yang NG ,  Chew Yeek LAU ,  Swee Kah LEE ,  Joseph Victor SOOSAI PRAKASAM ,  Hui Khin TAN

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/03 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/11 ,  H01L21/56 ,  H01L23/49838 ,  H01L24/13 ,  H01L2924/141 ,  H01L2224/16225 ,  H01L2924/182

Abstract: A method of manufacturing a package is disclosed. In one example, the method comprises applying a metallic connection structure, which comprises a solder or sinter material, on a sacrificial carrier. An electronic component is mounted on the metallic connection structure. At least part of the electronic component and of the metallic connection structure is encapsulated. Thereafter, the sacrificial carrier is removed to thereby expose at least part of the metallic connection structure.

公开(公告)号：US20170256472A1

公开(公告)日：2017-09-07

申请号：US15448018

申请日：2017-03-02

Applicant: Infineon Technologies AG

Inventor： Sook Woon CHAN ,  Chau Fatt CHIANG ,  Kok Yau CHUA ,  Soon Lock GOH ,  Swee Kah LEE ,  Joachim MAHLER ,  Mei Chin NG ,  Beng Keh SEE ,  Guan Choon Matthew Nelson TEE

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/552 ,  H01L21/56 ,  C23C18/16 ,  C09D5/00 ,  C09D201/00 ,  C23C18/34 ,  C23C18/18 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/3192 ,  C09D5/002 ,  C09D5/24 ,  C09D201/00 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/1637 ,  C23C18/166 ,  C23C18/1689 ,  C23C18/182 ,  C23C18/1831 ,  C23C18/1834 ,  C23C18/1837 ,  C23C18/1868 ,  C23C18/1879 ,  C23C18/1882 ,  C23C18/34 ,  H01L21/56 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16501 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.

公开(公告)号：US20220278085A1

公开(公告)日：2022-09-01

申请号：US17677055

申请日：2022-02-22

Applicant: Infineon Technologies AG

Inventor： Chau Fatt CHIANG ,  Paul Armand Asentista CALO ,  Chan Lam CHA ,  Kok Yau CHUA ,  Chee Hong LEE ,  Swee Kah LEE ,  Theng Chao LONG ,  Jayaganasan NARAYANASAMY ,  Khay Chwan Andrew SAW

IPC: H01L25/16 ,  H01L23/13 ,  H01L21/48 ,  H01L25/00 ,  H01L25/10 ,  H01L23/498

Abstract: The method for fabricating an electrical module is disclosed. In one example, the method includes providing a bottom unit comprising a plateable encapsulant. Selective areas of the bottom unit are activated thereby turning them into electrically conductive regions. At least one electrical device comprising external contact elements is provided. The method includes placing the electrical device on the bottom unit so that the external contact elements are positioned above at least a first subset of the electrically conductive regions, and performing a plating process on the electrically conductive regions for generating plated regions and for electrically connecting the external contact elements with at least a first subset of the plated regions.

公开(公告)号：US20190341324A1

公开(公告)日：2019-11-07

申请号：US16514853

申请日：2019-07-17

Applicant: Infineon Technologies AG

Inventor： Sook Woon CHAN ,  Chau Fatt CHIANG ,  Kok Yau CHUA ,  Soon Lock GOH ,  Swee Kah LEE ,  Joachim MAHLER ,  Mei Chin NG ,  Beng Keh SEE ,  Guan Choon Matthew Nelson TEE

IPC: H01L23/31 ,  H01L23/29 ,  C23C18/18 ,  C23C18/16 ,  C09D5/24 ,  C09D5/00 ,  C09D201/00 ,  H01L21/56 ,  C23C18/34 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00

Abstract: A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.

公开(公告)号：US20150344730A1

公开(公告)日：2015-12-03

申请号：US14287231

申请日：2014-05-27

Applicant: Infineon Technologies AG

Inventor： Swee Kah LEE ,  Joachim MAHLER ,  Chew Theng TAI ,  Yik Yee TAN ,  Soon Lock GOH ,  Poh Cheng LIM ,  Jagen KRISHNAN ,  Peh Hean TEH

IPC: C09D179/04 ,  H01L23/29 ,  H01L21/56 ,  C09D163/00 ,  C09D5/08

CPC classification number: C09D179/04 ,  C08G14/06 ,  C09D5/002 ,  C09D5/08 ,  C09D161/34 ,  C09D163/00 ,  H01L21/565 ,  H01L23/296 ,  H01L23/3142 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  C08K5/544 ,  C08L63/00

Abstract: A primer composition is provided. The primer composition includes at least one bi- or multi-functional benzoxazine compound; and at least one compound including a functional group having affinity for a metallic surface, and a cross-linkable group. A method of forming a primer layer on a semiconductor device, and a method of encapsulating a semiconductor device are also provided.

Abstract translation: 提供底漆组合物。 底漆组合物包括至少一种双官能或多官能苯并恶嗪化合物; 和至少一种包含对金属表面具有亲和性的官能团的化合物和可交联基团。 还提供了在半导体器件上形成底漆层的方法以及封装半导体器件的方法。