专利检索 cpc:"H01L2224/13686" 第 1 页

1.

发明授权
Package structure and manufacturing method thereof 有权

公开(公告)号：US12051639B2

公开(公告)日：2024-07-30

申请号：US17684416

申请日：2022-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chiang Tsao , Chao-Wei Chiu , Jen-Jui Yu , Hsiu-Jen Lin , Ching-Hua Hsieh

IPC分类号： H01L23/498 , H01L21/48 , H01L23/00 , H01L25/065 , H01L25/10 , H01L23/367 , H01L23/538

CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/4867 , H01L24/13 , H01L24/14 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L23/3675 , H01L23/49822 , H01L23/5383 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/92 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1357 , H01L2224/13582 , H01L2224/13611 , H01L2224/13639 , H01L2224/13655 , H01L2224/13686 , H01L2224/1403 , H01L2224/14505 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2224/92125 , H01L2225/06517 , H01L2225/1058 , H01L2924/04941 , H01L2924/04953 , H01L2924/0665

摘要： A package structure includes a first package, a second package, a conductive spacer, and a flux portion. The first package includes a semiconductor die. The second package is stacked to the first package. The conductive spacer is disposed between and electrically couples the first package and the second package. The flux portion is disposed between and electrically couples the first package and the conductive spacer, where the flux portion includes a first portion and a second portion separating from the first portion by a gap, and the first portion and the second portion are symmetric about an extending direction of the gap. The gap is overlapped with the conductive spacer.

2.

发明申请
MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER 审中-公开

公开(公告)号：US20180076160A1

公开(公告)日：2018-03-15

申请号：US15813311

申请日：2017-11-15

申请人： International Business Machines Corporation

发明人： Brian M. Erwin , Brittany L. Hedrick , Nicholas A. Polomoff , TaeHo Kim , Matthew E. Souter

IPC分类号： H01L23/00

CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03632 , H01L2224/0381 , H01L2224/0382 , H01L2224/04105 , H01L2224/05647 , H01L2224/11009 , H01L2224/11632 , H01L2224/1181 , H01L2224/1182 , H01L2224/131 , H01L2224/13147 , H01L2224/13686 , H01L2924/05042 , H01L2924/00014 , H01L2924/014 , H01L2924/01029 , H01L2924/053

摘要： A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

3.

发明申请
Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices 审中-公开

公开(公告)号：US20170229421A1

公开(公告)日：2017-08-10

申请号：US15497408

申请日：2017-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Jen Tseng , Yen-Liang Lin , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii

IPC分类号： H01L23/00

CPC分类号： H01L24/15 , H01L21/02118 , H01L21/0273 , H01L21/283 , H01L21/44 , H01L21/47 , H01L21/563 , H01L23/3142 , H01L23/3192 , H01L23/488 , H01L23/49816 , H01L23/5283 , H01L24/03 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/02333 , H01L2224/0347 , H01L2224/0401 , H01L2224/05567 , H01L2224/05624 , H01L2224/1146 , H01L2224/11472 , H01L2224/13005 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13017 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13565 , H01L2224/1357 , H01L2224/13686 , H01L2224/16058 , H01L2224/16238 , H01L2224/73104 , H01L2224/81191 , H01L2224/81192 , H01L2224/81345 , H01L2224/81815 , H01L2224/8182 , H01L2224/83104 , H01L2224/94 , H01L2225/06513 , H01L2924/00014 , H01L2924/15787 , H01L2924/181 , H01L2924/3841 , H01L2224/11 , H01L2924/00012 , H01L2924/207 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552 , H01L2924/00

摘要： Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. A method of forming a device includes forming a conductive trace over a first substrate, the conductive trace having first tapering sidewalls, forming a conductive bump over a second substrate, the conductive bump having second tapering sidewalls and a first surface distal the second substrate, and attaching the conductive bump to the conductive trace via a solder region. The solder region extends from the first surface of the conductive bump to the first substrate, and covers the first tapering sidewalls of the conductive trace. The second tapering sidewalls of the conductive bump are free of the solder region.

4.

发明申请
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法

公开(公告)号：US20160358875A1

公开(公告)日：2016-12-08

申请号：US15239745

申请日：2016-08-17

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Yu-Hsiang HSIAO , Chiu-Wen LEE , Ping-Feng YANG , Kwang-Lung LIN

IPC分类号： H01L23/00 , H01L25/00 , C22C9/02 , B23K35/26 , B23K1/00 , C22C13/00 , H01L25/065 , B23K35/30

CPC分类号： H01L24/13 , B23K1/0016 , B23K35/262 , B23K35/302 , B23K2101/40 , C22C9/02 , C22C13/00 , H01L24/05 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05147 , H01L2224/05572 , H01L2224/1182 , H01L2224/13025 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13686 , H01L2224/16146 , H01L2224/16503 , H01L2224/16507 , H01L2224/81193 , H01L2224/8181 , H01L2224/81815 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2225/06582 , H01L2924/01029 , H01L2924/01327 , H01L2924/014 , H01L2924/181 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014

摘要： A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

摘要翻译： 半导体器件包括第一电路层，邻近第一电路层设置的铜柱，第二电路层和焊料层。第二电路层包括电接触和设置在电接触上的表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。焊料层设置在铜柱和表面光洁剂层之间。焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的两种或更多种的组合，第二IMC包括金和锡的组合，钯的组合和锡，或两者。

5.

发明申请
Bump Structure and Method of Forming Same 审中-公开
标题翻译：凸块结构及其形成方法

公开(公告)号：US20150357301A1

公开(公告)日：2015-12-10

申请号：US14828147

申请日：2015-08-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guan-Yu Chen , Yu-Wei Lin , Yu-Jen Tseng , Tin-Hao Kuo , Chen-Shien Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/02 , H01L21/4853 , H01L21/76885 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02125 , H01L2224/02141 , H01L2224/02145 , H01L2224/0215 , H01L2224/0401 , H01L2224/05114 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05647 , H01L2224/10125 , H01L2224/11013 , H01L2224/11019 , H01L2224/1112 , H01L2224/11462 , H01L2224/11472 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13023 , H01L2224/13026 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13551 , H01L2224/13564 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13686 , H01L2224/1369 , H01L2224/14051 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/16503 , H01L2224/81007 , H01L2224/81143 , H01L2224/81191 , H01L2224/81203 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/8181 , H01L2224/81895 , H01L2224/8192 , H01L2224/81948 , H01L2225/06513 , H01L2924/04941 , H01L2924/07025 , H01L2924/181 , H01L2924/301 , H01L2924/35 , Y10T29/49144 , H01L2924/00014 , H01L2924/014 , H01L2924/05432 , H01L2924/053 , H01L2924/00 , H01L2924/00012

摘要： An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

摘要翻译： 轨迹（BOT）结构上的实施例凸块包括由集成电路支撑的接触元件，电耦合到接触元件的凸块下金属（UBM）特征，凸起下金属冶金特征上的金属凸块，以及衬底迹线衬底，通过焊接接头和金属间化合物耦合到金属凸块的衬底迹线，金属间化合物的第一横截面积与焊料接头的第二横截面积的比率大于百分之四十。

6.

发明申请
Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices 有权
标题翻译：半导体器件，其制造方法和封装半导体器件

公开(公告)号：US20140167253A1

公开(公告)日：2014-06-19

申请号：US13719019

申请日：2012-12-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Jen Tseng , Yen-Liang Lin , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii

IPC分类号： H01L23/528 , H01L21/768 , H01L23/00 , H01L23/532

CPC分类号： H01L24/15 , H01L21/02118 , H01L21/0273 , H01L21/283 , H01L21/44 , H01L21/47 , H01L21/563 , H01L23/3142 , H01L23/3192 , H01L23/488 , H01L23/49816 , H01L23/5283 , H01L24/03 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/02333 , H01L2224/0347 , H01L2224/0401 , H01L2224/05567 , H01L2224/05624 , H01L2224/1146 , H01L2224/11472 , H01L2224/13005 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13017 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13565 , H01L2224/1357 , H01L2224/13686 , H01L2224/16058 , H01L2224/16238 , H01L2224/73104 , H01L2224/81191 , H01L2224/81192 , H01L2224/81345 , H01L2224/81815 , H01L2224/8182 , H01L2224/83104 , H01L2224/94 , H01L2225/06513 , H01L2924/00014 , H01L2924/15787 , H01L2924/181 , H01L2924/3841 , H01L2224/11 , H01L2924/00012 , H01L2924/207 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552 , H01L2924/00

摘要： Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width.

摘要翻译： 公开了半导体器件，其制造方法和封装的半导体器件。在一个实施例中，半导体器件包括衬底和设置在衬底上的导电迹线。每个导电迹线具有靠近衬底的底部区域和与底部区域相对的顶部区域。顶部区域具有第一宽度，底部区域具有第二宽度。第二宽度大于第一宽度。

7.

发明申请
Connector Design for Packaging Integrated Circuits 有权
标题翻译：封装集成电路连接器设计

公开(公告)号：US20140131864A1

公开(公告)日：2014-05-15

申请号：US14161111

申请日：2014-01-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu , Ying Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Jing-Cheng Lin , Shang-Yun Hou , Shin-Puu Jeng

IPC分类号： H01L23/00 , H01L25/00 , H01L25/04

CPC分类号： H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00

摘要： A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

摘要翻译： 一种器件包括具有顶表面的顶部电介质层。金属柱在顶部介电层的顶表面上具有一部分。在金属柱的侧壁上形成非润湿层，其中非润湿层不能熔化到熔融焊料上。焊料区域设置在金属柱上并电耦合到金属柱。

8.

发明申请
SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件

公开(公告)号：US20140061920A1

公开(公告)日：2014-03-06

申请号：US14078022

申请日：2013-11-12

申请人： PANASONIC CORPORATION

发明人： Hiroshige HIRANO , Yutaka ITOH , Hiroyuki ISHIDA , Kazuhiro ISHIKAWA

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76885 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/0382 , H01L2224/0401 , H01L2224/04042 , H01L2224/05023 , H01L2224/05084 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05541 , H01L2224/05568 , H01L2224/05644 , H01L2224/10126 , H01L2224/1146 , H01L2224/1147 , H01L2224/13 , H01L2224/13018 , H01L2224/13083 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/13565 , H01L2224/1357 , H01L2224/13686 , H01L2924/00014 , H01L2224/05005 , H01L2924/05042 , H01L2924/00012

摘要： A semiconductor device includes: a first insulating film formed on a semiconductor substrate; a first interconnect formed on the first insulating film; a second insulating film formed on the first insulating film to cover the first interconnect; and a second interconnect formed on the second insulating film. The second interconnect includes a barrier layer formed on the second insulating film, and a plated layer formed on the barrier layer. The barrier layer prevents diffusion of atoms forming the plated layer into the second insulating film, and has a greater width than the plated layer.

摘要翻译： 半导体器件包括：形成在半导体衬底上的第一绝缘膜; 形成在第一绝缘膜上的第一互连; 形成在所述第一绝缘膜上以覆盖所述第一互连的第二绝缘膜; 以及形成在所述第二绝缘膜上的第二互连。第二互连包括形成在第二绝缘膜上的阻挡层和形成在阻挡层上的镀层。阻挡层防止形成镀层的原子扩散到第二绝缘膜中，并且具有比镀层更大的宽度。

9.

发明申请
SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件

公开(公告)号：US20130140696A1

公开(公告)日：2013-06-06

申请号：US13759833

申请日：2013-02-05

申请人： PANASONIC CORPORATION

发明人： Nobuo AOI

IPC分类号： H01L23/498

CPC分类号： H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05023 , H01L2224/05147 , H01L2224/05568 , H01L2224/05647 , H01L2224/10145 , H01L2224/1145 , H01L2224/11462 , H01L2224/1147 , H01L2224/11622 , H01L2224/11827 , H01L2224/11831 , H01L2224/13082 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13565 , H01L2224/1357 , H01L2224/13686 , H01L2224/1601 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/81937 , H01L2924/00014 , H01L2924/3841 , H01L2924/05442 , H01L2224/05552

摘要： A semiconductor device includes a first substrate; a plurality of first electrodes formed on the first substrate; and a first insulating film formed on sidewalls of the plurality of first electrodes. The first insulating film is formed not to fill spaces between the plurality of first electrodes.

摘要翻译： 半导体器件包括第一衬底; 形成在所述第一基板上的多个第一电极; 以及形成在所述多个第一电极的侧壁上的第一绝缘膜。第一绝缘膜形成为不填充多个第一电极之间的空间。