公开(公告)号：US20220199464A1

公开(公告)日：2022-06-23

申请号：US17128866

申请日：2020-12-21

Applicant: Infineon Technologies AG

Inventor： Stephan VOSS ,  Alexander BREYMESSER ,  Eva-Maria HOF ,  Mathias PLAPPERT ,  Carsten SCHAEFFER

IPC: H01L21/768 ,  H01L23/52 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a metallic layer may be formed over a semiconductor substrate. An anti-reflective layer may be formed over the metallic layer. A passivation layer may be formed over the anti-reflective layer. An opening may be formed in the passivation layer to expose the anti-reflective layer.

公开(公告)号：US20250006814A1

公开(公告)日：2025-01-02

申请号：US18756389

申请日：2024-06-27

Applicant: Infineon Technologies AG

Inventor： Wolfgang LEHNERT ,  Fabian RASINGER ,  Thomas AICHINGER ,  Gerald RESCHER ,  Francisco Javier SANTOS RODRIGUEZ ,  Carsten SCHAEFFER ,  Armin TILKE

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/16 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78

Abstract: A method for forming an interface layer on a silicon carbide body comprises removing an oxide layer from a surface of a silicon carbide body to obtain a silicon carbide surface. The silicon carbide body comprises a source region of a first conductivity type and a body region of a second conductivity type. The method further comprises after removing the oxide layer, depositing an interface layer directly on the silicon carbide surface. The interface layer has a thickness of less or equal to 15 nm. The method further comprises forming an electrical insulator over the interface layer, and forming a gate electrode over the electrical insulator.

公开(公告)号：US20230274996A1

公开(公告)日：2023-08-31

申请号：US18105309

申请日：2023-02-03

Applicant: Infineon Technologies AG

Inventor： Stefan SCHWAB ,  Edward FÜRGUT ,  Edmund RIEDL ,  Harry SAX ,  Stefan KRIVEC ,  Manfred PFAFFENLEHNER ,  Carsten SCHAEFFER

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L21/56 ,  H01L23/3135 ,  H01L24/02 ,  H01L24/05 ,  H01L23/291

Abstract: A chip arrangement is provided. The chip arrangement may include a chip including a first main surface, wherein the first main surface includes an active area, a chip termination portion, and at least one contact pad. A first dielectric layer at least partially covers the chip termination portion and the active area, and at least partially exposes the at least one contact pad, and a second dielectric layer formed by atomic layer deposition over the first dielectric layer and over the at least one contact pad.

公开(公告)号：US20240347456A1

公开(公告)日：2024-10-17

申请号：US18606152

申请日：2024-03-15

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav JOSHI ,  Carsten SCHAEFFER

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L29/1608 ,  H01L29/66045 ,  H01L29/7827

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. A first wiring level is arranged over the first surface. The first wiring level includes a first lower source or emitter pad and a second lower source or emitter pad. A second wiring level is arranged over the first wiring level. The second wiring level includes a gate pad and a source or emitter pad. The source or emitter pad of the second wiring level is electrically connected to the first lower source or emitter pad and to the second lower source or emitter pad of the first wiring level. The first wiring level further includes a gate line laterally arranged between the first lower source or emitter pad and the second lower source or emitter pad. The gate line is vertically arranged between the source or emitter pad of the second wiring level and the first surface. The gate line is electrically insulated from the source or emitter pad of the second wiring level by an intermediate dielectric structure.

公开(公告)号：US20230154978A1

公开(公告)日：2023-05-18

申请号：US17526490

申请日：2021-11-15

Applicant: Infineon Technologies AG

Inventor： Carsten SCHAEFFER ,  Patrick HANEKAMP ,  Oliver HUMBEL ,  Angelika KOPROWSKI ,  Wolfgang LEHNERT ,  Francisco Javier SANTOS RODRIGUEZ

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L29/0638 ,  H01L29/402 ,  H01L21/0217 ,  H01L21/02118 ,  H01L21/0228

Abstract: A semiconductor device and a method of forming a semiconductor device are provided. In an embodiment, the semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.

公开(公告)号：US20200013859A1

公开(公告)日：2020-01-09

申请号：US16502451

申请日：2019-07-03

Applicant: Infineon Technologies AG

Inventor： Carsten SCHAEFFER ,  Alexander Breymesser ,  Bernhand Goller ,  Ronny Kern ,  Matteo Piccin ,  Roland Rupp ,  Francisco Javier Santos Rodriguez

IPC: H01L29/16 ,  H01L21/04 ,  H01L21/784 ,  H01L21/683 ,  H01L29/66

Abstract: According to an embodiment of a method described herein, a silicon carbide substrate is provided that includes a plurality of device regions. A front side metallization may be provided at a front side of the silicon carbide substrate. The method may further comprise providing an auxiliary structure at a backside of the silicon carbide substrate. The auxiliary structure includes a plurality of laterally separated metal portions. Each metal portion is in contact with one device region of the plurality of device regions.