公开(公告)号：US20250113592A1

公开(公告)日：2025-04-03

申请号：US18374895

申请日：2023-09-29

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav JOSHI ,  Fabian RASINGER ,  Kristijan Luka MLETSCHNIG ,  Romain ESTEVE ,  Caspar LEENDERTZ

IPC: H01L27/07 ,  H01L29/423 ,  H01L29/78 ,  H01L29/872

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a semiconductor body including a first doped region of a first conductivity type and a second doped region of a second conductivity type. The semiconductor device may include a metal structure, in the semiconductor body, overlying the second doped region. The metal structure may include a first sidewall adjacent a first portion of the first doped region, a second sidewall adjacent a second portion of the first doped region, and a third sidewall adjacent the second doped region. The semiconductor device may include a Schottky contact including a junction of the third sidewall of the metal structure with the second doped region.

公开(公告)号：US20230024105A1

公开(公告)日：2023-01-26

申请号：US17869567

申请日：2022-07-20

Applicant: Infineon Technologies AG

Inventor： Werner SCHUSTEREDER ,  Ravi Keshav JOSHI ,  Hans-Joachim SCHULZE ,  Ralf SIEMIENIEC ,  Axel KOENIG

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45

Abstract: The present disclosure relates to methods of manufacturing Ohmic contacts on a silicon carbide (SiC) substrate including providing a 4H—SiC or 6H—SiC substrate, implanting dopants into a surface region of the 4H—SiC or 6H—SiC substrate, annealing the implanted surface regions to form a 3C—SiC layer, and depositing a metal layer on the 3C—SiC layer. An implanting sequence of the implantation of dopants includes a plurality of plasma deposition acts with implantation energy levels including at least two different implantation energy levels. The implantation energy levels and one or more implantation doses of the plurality of plasma deposition acts are selected to form a 3C—SiC layer in the surface region of the 4H—SiC or 6H—SiC substrate during the annealing act. A method of manufacturing a semiconductor device having a structure including at least three layers including a 4H—SiC or 6H—SiC layer, a 3C—SiC layer, and a metal layer, by applying one or more of the techniques described herein, and semiconductor devices obtained with one or more of the techniques described herein are described.

公开(公告)号：US20240055256A1

公开(公告)日：2024-02-15

申请号：US18231176

申请日：2023-08-07

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav JOSHI ,  Kristijan Luka MLETSCHNIG ,  Axel KÖNIG ,  Gregor LANGER

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/04 ,  H01L29/45

CPC classification number: H01L21/0485 ,  H01L29/1608 ,  H01L29/04 ,  H01L29/45

Abstract: The disclosure relates to a method for manufacturing a contact on a silicon carbide semiconductor substrate and to a silicon carbide semiconductor device comprising a crystalline silicon carbide semiconductor substrate and a contact layer directly in contact with the silicon carbide semiconductor substrate surface and having, at an interface to the semiconductor substrate, a contact phase portion comprising at least a metal, silicon, and carbon. The method comprises the acts of providing a crystalline silicon carbide semiconductor substrate, depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate, and irradiating at least a part of the silicon carbide semiconductor substrate and at least a part of the metallic contact material layer at their interface with at least one thermal annealing laser beam, thereby generating a contact phase portion at the interface, wherein the contact phase portion comprises at least a metal, silicon, and carbon.

公开(公告)号：US20240030032A1

公开(公告)日：2024-01-25

申请号：US18225030

申请日：2023-07-21

Applicant: Infineon Technologies AG

Inventor： Saurabh ROY ,  Ravi Keshav JOSHI ,  Hans-Joachim SCHULZE ,  Bernhard GOLLER ,  Daria KRASNOZHON

IPC: H01L21/04 ,  H01L29/45 ,  H01L29/16 ,  H01L21/268

CPC classification number: H01L21/0485 ,  H01L29/45 ,  H01L29/1608 ,  H01L21/268

Abstract: The present disclosure generally relates to a method of manufacturing a contact on a silicon carbide semiconductor substrate wherein the method comprises providing a 4H—SiC semiconductor substrate, irradiating a surface area of the 4H—SiC semiconductor substrate with a first thermal annealing laser beam, thereby generating a phase separation of the surface area comprising at least a 3C—SiC layer, and depositing a contact material onto the 3C—SiC layer to form a contact layer on the semiconductor substrate. The disclosure further relates to a silicon carbide semiconductor device with an Ohmic contact comprising a 4H—SiC semiconductor substrate, a 3C—SiC layer, and a contact layer directly in contact with the 3C—SiC layer at the semiconductor surface.

公开(公告)号：US20240347456A1

公开(公告)日：2024-10-17

申请号：US18606152

申请日：2024-03-15

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav JOSHI ,  Carsten SCHAEFFER

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L29/1608 ,  H01L29/66045 ,  H01L29/7827

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. A first wiring level is arranged over the first surface. The first wiring level includes a first lower source or emitter pad and a second lower source or emitter pad. A second wiring level is arranged over the first wiring level. The second wiring level includes a gate pad and a source or emitter pad. The source or emitter pad of the second wiring level is electrically connected to the first lower source or emitter pad and to the second lower source or emitter pad of the first wiring level. The first wiring level further includes a gate line laterally arranged between the first lower source or emitter pad and the second lower source or emitter pad. The gate line is vertically arranged between the source or emitter pad of the second wiring level and the first surface. The gate line is electrically insulated from the source or emitter pad of the second wiring level by an intermediate dielectric structure.

公开(公告)号：US20230238442A1

公开(公告)日：2023-07-27

申请号：US18097656

申请日：2023-01-17

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav JOSHI ,  Romain ESTEVE ,  Saurabh ROY ,  Bernhard GOLLER ,  Werner SCHUSTEREDER ,  Kristijan Luka MLETSCHNIG

IPC: H01L29/45 ,  H01L29/417 ,  H01L23/528 ,  H01L29/40 ,  H01L21/321

CPC classification number: H01L29/45 ,  H01L29/41741 ,  H01L23/528 ,  H01L29/401 ,  H01L21/321

Abstract: A semiconductor device includes a semiconductor substrate and a metal nitride layer above the semiconductor substrate. The metal nitride layer forms at least one interface region with the semiconductor substrate. The at least one interface region includes a first portion of the semiconductor substrate, a first portion of the metal nitride layer, and an interface between the first portion of the semiconductor substrate and the first portion of the metal nitride layer. A concentration of nitrogen content at the first portion of the metal nitride layer is higher than a concentration of nitrogen content at a second portion, of the metal nitride layer, outside the interface region. A distribution of nitrogen content throughout the metal nitride layer may have a maximum concentration at the first portion of the metal nitride layer. Alternatively and/or additionally, a method for producing such a semiconductor device is provided herein.

公开(公告)号：US20220262906A1

公开(公告)日：2022-08-18

申请号：US17671838

申请日：2022-02-15

Applicant: Infineon Technologies AG

Inventor： Ralf SIEMIENIEC ,  Thomas AICHINGER ,  Ravi Keshav JOSHI ,  Werner SCHUSTEREDER

IPC: H01L29/16 ,  H01L29/423 ,  H01L21/04 ,  H01L29/78 ,  H01L29/66

Abstract: A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer.