公开(公告)号：US11616032B2

公开(公告)日：2023-03-28

申请号：US17152988

申请日：2021-01-20

Applicant: Infineon Technologies AG

Inventor： Daniel Maurer ,  Christof Altstaetter ,  Thomas Beyreder ,  Oliver Blank ,  Jürgen Bostjancic ,  Andreas Kleinbichler ,  Josef Liegl ,  Nicole Schulze-Ollmert

IPC: H01L23/00 ,  G01R31/28

Abstract: A semiconductor device includes a semiconductor substrate having a main surface over which a plurality of die pads and at least one alignment pad for optical process control for semiconductor wafer probing are arranged. The alignment pad has a hardness smaller than a hardness of the plurality of die pads.

公开(公告)号：US20170271446A1

公开(公告)日：2017-09-21

申请号：US15457833

申请日：2017-03-13

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Johannes Baumgartl ,  Oliver Blank ,  Oliver Hellmund ,  Martin Poelzl

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/78 ,  H01L29/78 ,  B81B7/00 ,  B81C1/00 ,  H01L29/40 ,  H01L29/10 ,  H01L21/683

CPC classification number: H01L29/0696 ,  B81B3/0072 ,  B81B7/008 ,  B81B2207/015 ,  B81C1/00246 ,  B81C2203/0707 ,  G01C19/5733 ,  G01P15/125 ,  H01L21/6835 ,  H01L21/78 ,  H01L29/02 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2221/68327

Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

公开(公告)号：US20150041816A1

公开(公告)日：2015-02-12

申请号：US14447896

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: The disclosure relates to a semiconductor device including a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

Abstract translation: 本公开涉及一种半导体器件，其包括在从第一表面延伸到半导体本体的第一沟槽中具有IGFET的第一表面，第一表面，包括多晶硅的栅电极结构的半导体本体。 所述器件还包括半导体元件，所述半导体元件与所述IGFET的栅电极结构不同，并且在从所述第一表面延伸到所述半导体本体的第二沟槽中包括多晶硅，其中所述IGFET的多晶硅和所述半导体元件 不同之处在与半导体本体的第一表面相邻的绝缘层的顶侧下方。

公开(公告)号：US09356141B2

公开(公告)日：2016-05-31

申请号：US14447896

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L27/11 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  H01L29/423 ,  H01L29/8605 ,  H01L29/861 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: The disclosure relates to a semiconductor device including a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

Abstract translation: 本公开涉及一种半导体器件，其包括在从第一表面延伸到半导体本体的第一沟槽中具有IGFET的第一表面，第一表面，包括多晶硅的栅电极结构的半导体本体。 所述器件还包括半导体元件，所述半导体元件与所述IGFET的栅电极结构不同，并且在从所述第一表面延伸到所述半导体本体的第二沟槽中包括多晶硅，其中所述IGFET的多晶硅和所述半导体元件 不同之处在与半导体本体的第一表面相邻的绝缘层的顶侧下方。

公开(公告)号：US09917160B2

公开(公告)日：2018-03-13

申请号：US15098789

申请日：2016-04-14

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L29/04 ,  H01L27/11526 ,  H01L29/423 ,  H01L29/8605 ,  H01L29/861 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

公开(公告)号：US20240194580A1

公开(公告)日：2024-06-13

申请号：US18521001

申请日：2023-11-28

Applicant: Infineon Technologies AG

Inventor： Susanne Schulte ,  Scott David Wallace ,  Oliver Blank

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/45005 ,  H01L2224/4502 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/13055 ,  H01L2924/1306

Abstract: A power semiconductor device includes a semiconductor substrate. A signal routing structure is disposed above the semiconductor substrate. The signal routing structure comprises a specific metal. A solderable power pad forms a power terminal of the power semiconductor device. The solderable power pad comprises the specific metal. An electrically insulating dielectric passivation layer is disposed between the solderable power pad and the signal routing structure.

公开(公告)号：US20210242148A1

公开(公告)日：2021-08-05

申请号：US17152988

申请日：2021-01-20

Applicant: Infineon Technologies AG

Inventor： Daniel Maurer ,  Christof Altstaetter ,  Thomas Beyreder ,  Oliver Blank ,  Jürgen Bostjancic ,  Andreas Kleinbichler ,  Josef Liegl ,  Nicole Schulze-Ollmert

IPC: H01L23/00 ,  G01R31/28

Abstract: A semiconductor device includes a semiconductor substrate having a main surface over which a plurality of die pads and at least one alignment pad for optical process control for semiconductor wafer probing are arranged. The alignment pad has a hardness smaller than a hardness of the plurality of die pads.

公开(公告)号：US10121859B2

公开(公告)日：2018-11-06

申请号：US15457833

申请日：2017-03-13

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Johannes Baumgartl ,  Oliver Blank ,  Oliver Hellmund ,  Martin Poelzl

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/78 ,  H01L21/68 ,  H01L21/683 ,  B81B7/00 ,  B81C1/00 ,  H01L29/40 ,  H01L29/78

Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

公开(公告)号：US20160233308A1

公开(公告)日：2016-08-11

申请号：US15098789

申请日：2016-04-14

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L29/40 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

Abstract translation: 半导体器件包括半导体本体，其具有第一表面，包括多晶硅的栅极电极结构，所述第一表面包括多晶硅，所述第一表面在从所述第一表面延伸到所述半导体本体中的第一沟槽中具有IGFET。 所述器件还包括半导体元件，所述半导体元件与所述IGFET的栅电极结构不同，并且在从所述第一表面延伸到所述半导体本体的第二沟槽中包括多晶硅，其中所述IGFET的多晶硅和所述半导体元件 不同之处在与半导体本体的第一表面相邻的绝缘层的顶侧下方。

公开(公告)号：US20230178615A1

公开(公告)日：2023-06-08

申请号：US18072965

申请日：2022-12-01

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Hans-Joachim Schulze ,  Oliver Blank ,  Josef Anton Moser ,  Thomas Aichinger

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/1095 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/7813

Abstract: A power transistor device includes a semiconductor substrate, a gate trench extending into the semiconductor substrate, a transistor gate provided in the gate trench, and an insulating structure formed between the transistor gate and a side wall of the gate trench. The insulating structure is configured to electrically insulate the transistor gate from a channel region which extends along the side wall of the gate trench. The insulating structure includes a layer of piezoelectric material.