公开(公告)号：US11139389B2

公开(公告)日：2021-10-05

申请号：US15427968

申请日：2017-02-08

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A Young

IPC: H01L29/66 ,  H03K19/16 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

公开(公告)号：US09391262B1

公开(公告)日：2016-07-12

申请号：US14139528

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Ian A Young

IPC: H01L29/82 ,  H01L43/04

CPC classification number: H01L43/04 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: Described are Spin Hall Magnetic Random Access Memory (MRAM) cells and arrays. In one embodiment, an apparatus includes a nanomagnet having a cross-sectional area and a spin Hall effect (SHE) material. The SHE material is coupled to a subset of the cross-sectional area of the nanomagnet.

Abstract translation: 描述了旋转霍尔磁随机存取存储器（MRAM）单元和阵列。 在一个实施例中，装置包括具有横截面积和旋转霍尔效应（SHE）材料的纳米磁体。 SHE材料耦合到纳米磁体的横截面积的子集。

公开(公告)号：US11056593B2

公开(公告)日：2021-07-06

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A Young

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/18 ,  H01L21/3105 ,  H01L21/8252

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.