公开(公告)号：US20180331043A1

公开(公告)日：2018-11-15

申请号：US15774257

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Zhiguo QIAN ,  Kemal AYGUN ,  Yidnekachew S. MEKONNEN ,  Gregorio R. MURTAGIAN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Jeff C. MORRISS

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/552

CPC classification number: H01L23/5384 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L24/00 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.

公开(公告)号：US20200066641A1

公开(公告)日：2020-02-27

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Richard J. DISCHLER ,  Jeff C. MORRISS ,  Zhiguo QIAN ,  Wilfred GOMES ,  Yu Amos ZHANG ,  Ram S. VISWANATH ,  Rajasekaran SWAMINATHAN ,  Sriram SRINIVASAN ,  Yidnekachew S. MEKONNEN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Mathew J. MANUSHAROW

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/60

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.