公开(公告)号：US11588102B2

公开(公告)日：2023-02-21

申请号：US16322890

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Rafael Rios ,  Jack T. Kavalieros ,  Shriram Shivaraman

IPC: H01L45/00 ,  H01L27/24

Abstract: Embodiments include a resistive random access memory (RRAM) storage cell, having a resistive switching material layer and a semiconductor layer between two electrodes, where the semiconductor layer serves as an OEL. In addition, the RRAM storage cell may be coupled with a transistor to form a RRAM memory cell. The RRAM memory cell may include a semiconductor layer as a channel for the transistor, and also shared with the storage cell as an OEL for the storage cell. A shared electrode may serve as a source electrode of the transistor and an electrode of the storage cell. In some embodiments, a dielectric layer may be shared between the transistor and the storage cell, where the dielectric layer is a resistive switching material layer of the storage cell.

公开(公告)号：US20210193814A1

公开(公告)日：2021-06-24

申请号：US16075953

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Gilbert W. Dewey ,  Rafael Rios ,  Van H. Le ,  Jack T. Kavalieros

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/267 ,  H01L29/417 ,  H01L21/02 ,  H01L21/465 ,  H01L29/66

Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

公开(公告)号：US11031503B2

公开(公告)日：2021-06-08

申请号：US16329044

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Rafael Rios ,  Jack T. Kavalieros ,  Yih Wang ,  Shriram Shivaraman

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/50

Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.

公开(公告)号：US10593804B2

公开(公告)日：2020-03-17

申请号：US16108610

申请日：2018-08-22

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Rafael Rios ,  Fahmida Ferdousi ,  Kelin J. Kuhn

IPC: H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/10 ,  H01L29/786

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

公开(公告)号：US10580899B2

公开(公告)日：2020-03-03

申请号：US15405899

申请日：2017-01-13

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L21/268 ,  H01L29/78 ,  B82Y40/00

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US10249742B2

公开(公告)日：2019-04-02

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. Le ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Ashish Agrawal ,  Matthew V. Metz ,  Willy Rachmady ,  Marc C. French ,  Jack T. Kavalieros ,  Rafael Rios ,  Seiyon Kim ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  James M. Powers ,  Sherry R. Taft

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US10121856B2

公开(公告)日：2018-11-06

申请号：US15859226

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/3115 ,  H01L29/08 ,  H01L29/423 ,  B82Y40/00

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US10115822B2

公开(公告)日：2018-10-30

申请号：US14909981

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Rafael Rios ,  Roza Kotlyar ,  Kelin Kuhn

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L21/285 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.

公开(公告)号：US20180181175A1

公开(公告)日：2018-06-28

申请号：US15392559

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Rafael Rios ,  Somnath Paul ,  Muhammad M. Khellah

IPC: G06F1/26 ,  H03K3/356 ,  H03K3/012 ,  G06F1/32

Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

公开(公告)号：US09947805B2

公开(公告)日：2018-04-17

申请号：US15151381

申请日：2016-05-10

Applicant: Intel Corporation

Inventor： Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

IPC: H01H51/22 ,  H01L29/84 ,  H01H59/00 ,  B82Y10/00 ,  H01H1/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01H9/02

CPC classification number: H01L29/84 ,  B82Y10/00 ,  H01H1/0094 ,  H01H9/0271 ,  H01H59/0009 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.