公开(公告)号：US20160324487A1

公开(公告)日：2016-11-10

申请号：US14779513

申请日：2014-11-27

Applicant: INTEL CORPORATION

Inventor： Mao GUO ,  Junfeng ZHAO ,  Michael P. SKINNER ,  Ke XIAO ,  Jiamiao TANG ,  Bin LIU ,  Li DENG

IPC: A61B5/00 ,  G08B5/22 ,  A61B7/00 ,  A61B5/107 ,  A61B5/11 ,  H04Q9/00 ,  A61B5/08

CPC classification number: A61B5/746 ,  A61B5/0022 ,  A61B5/0816 ,  A61B5/1072 ,  A61B5/1118 ,  A61B5/4815 ,  A61B5/486 ,  A61B5/6804 ,  A61B5/6823 ,  A61B5/6831 ,  A61B5/7405 ,  A61B5/7455 ,  A61B7/00 ,  A61B2562/0219 ,  A61B2562/0247 ,  A61B2562/04 ,  A61B2562/063 ,  A61B2562/166 ,  G08B3/10 ,  G08B5/224 ,  G08B6/00 ,  G08B21/0269 ,  G08B21/0277 ,  G08B21/0283 ,  H04Q9/00 ,  H04Q2209/43

Abstract: Embodiments described herein may fully integrate personal computing and health care into a wearable waistband having a length sensor, a pressure sensor, and a motion sensor; or into a wearable “mesh” having an array of sound sensors, which will create convenient and seamless access to a personal computer and biofeedback of the wearer. Such biofeedback from the waistband may include determining respiration rate, waist length, food quantity of a meal, sitting or sleep time, and frequency of visits to the bathroom. Such biofeedback from the mesh or array may include determining whether there is or has been damage or other issues of the heart, lungs, bones, joints, jaw, throat, arteries, digestive tract, and the like. Such biofeedback may also detect whether whether a person has an allergic reaction at a location, is drinking (and what volume of fluid), is walking, is jogging or is running.

Abstract translation: 本文描述的实施例可以将个人计算和健康护理完全集成到具有长度传感器，压力传感器和运动传感器的可穿戴腰带中; 或具有声音传感器阵列的可穿戴的“网状”，其将创建便利且无缝地访问个人计算机和穿戴者的生物反馈。 来自腰带的这种生物反馈可以包括确定呼吸速率，腰围长度，膳食的食物数量，坐着或睡眠时间以及访问浴室的频率。 来自网状物或阵列的这种生物反馈可以包括确定是否存在心脏，肺，骨骼，关节，下颌，咽喉，动脉，消化道等的损伤或其它问题。 这种生物反馈还可以检测一个人是否在某个地点发生过敏反应，正在饮酒（以及什么体积的流体）正在步行，正在慢跑或跑步。

公开(公告)号：US20200066701A1

公开(公告)日：2020-02-27

申请号：US16326901

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Mao GUO

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus is described that includes a semiconductor chip package. The semiconductor chip package includes a plurality of stacked semiconductor chips. The plurality of stacked semiconductor chips are stacked with a lateral offset, wherein, the lateral offset exposes first wirebond pads of the plurality of stacked semiconductor chips. The semiconductor chip package further includes a substrate interposer having second wirebond pads. The semiconductor chip package further includes wirebonds connecting the first wirebond pads and the second wirebond pads. The semiconductor chip package further includes a package substrate. The semiconductor chip package further includes vias that are electrically connected to the substrate interposer and a first surface of the package substrate. The semiconductor chip package further includes package level I/Os on a second surface of the package substrate that is opposite the first surface of the package substrate.

公开(公告)号：US20180374832A1

公开(公告)日：2018-12-27

申请号：US15777855

申请日：2015-12-25

Applicant: Intel Corporation

Inventor： Mao GUO

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48799 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48) formed on a first foundation layer (12). A loop of conductive wire (50-53) is wirebonded to the first conductive pad ((40, 41, 47, 48) of the first foundation layer (12). A mold cap (70) is formed on the first foundation layer (12). A via (90-93) is formed in the mold cap (70) to reach the conductive wire (50-53). A solder structure (80-83) is coupled to the conductive wire (50-53). A second package (100) is connected to the first package (10) by attaching a second solder structure (110-113) of a second package (100) to the first solder structure (80-83) of the first package (10).

公开(公告)号：US20180331004A1

公开(公告)日：2018-11-15

申请号：US15772483

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Mao GUO ,  John G. MEYERS ,  Yong SHE ,  Bin LIU ,  Lingyan L. TAN

IPC: H01L23/28 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/28 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).

公开(公告)号：US20180323172A1

公开(公告)日：2018-11-08

申请号：US15772478

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Mao GUO ,  Sireesha GOGINENI

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/48 ,  H01L23/13 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A package with improved solder joint reliability is disclosed. The package includes dummy beams with less rigidity and stiffness (relative to the die) that are placed in between the die and the substrate. The reduced rigidity and stiffness of the dummy beams significantly mitigates any die shadow effects on the solder joints. Also, because the die is attached to the dummy beams and does not directly contact the substrate itself, the die shadow effect from a rigid die is further reduced.