公开(公告)号：US20210151393A1

公开(公告)日：2021-05-20

申请号：US17158634

申请日：2021-01-26

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US11728265B2

公开(公告)日：2023-08-15

申请号：US16129711

申请日：2018-09-12

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian ,  Dilan Seneviratne ,  Yonggang Li ,  Sameer Paital ,  Darko Grujicic ,  Rengarajan Shanmugam ,  Melissa Wette ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00 ,  H01L27/01 ,  H01L23/64

CPC classification number: H01L23/5228 ,  H01L21/4846 ,  H01L21/76871 ,  H01L23/498 ,  H01L23/5226 ,  H01L23/647 ,  H01L24/09 ,  H01L27/016 ,  H01L28/24

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

公开(公告)号：US11728077B2

公开(公告)日：2023-08-15

申请号：US17482861

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498 ,  H01F17/00

CPC classification number: H01F1/20 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/2804 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01F2027/2809 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.

公开(公告)号：US10923443B2

公开(公告)日：2021-02-16

申请号：US16369708

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC: H01L23/495 ,  H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US11637171B2

公开(公告)日：2023-04-25

申请号：US16934873

申请日：2020-07-21

Applicant: Intel Corporation

Inventor： Shivasubramanian Balasubramanian ,  Dilan Seneviratne

IPC: H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  H01L27/08

Abstract: A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.

公开(公告)号：US20200312793A1

公开(公告)日：2020-10-01

申请号：US16369708

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D. Ecton

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US20200006463A1

公开(公告)日：2020-01-02

申请号：US16020271

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Shivasubramanian Balasubramanian ,  Dilan Seneviratne

IPC: H01L49/02 ,  H01L27/08 ,  H01L23/522 ,  H01L23/498

Abstract: A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.

公开(公告)号：US11158444B2

公开(公告)日：2021-10-26

申请号：US15894418

申请日：2018-02-12

Applicant: INTEL CORPORATION

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498 ,  H01F17/00

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.

公开(公告)号：US10756161B2

公开(公告)日：2020-08-25

申请号：US16020271

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Shivasubramanian Balasubramanian ,  Dilan Seneviratne

IPC: H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  H01L27/08

Abstract: A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.

公开(公告)号：US20190252102A1

公开(公告)日：2019-08-15

申请号：US15894418

申请日：2018-02-12

Applicant: INTEL CORPORATION

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01F1/20 ,  H01F27/2804 ,  H01F2027/2809 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.