公开(公告)号：US20230317660A1

公开(公告)日：2023-10-05

申请号：US17710518

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Zhaozhi Li ,  Feras Eid ,  Michael Baker ,  Wenhao Li ,  Pilin Liu ,  Johanna Swan

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/06 ,  H01L24/81 ,  H01L24/16 ,  H01L2224/1403 ,  H01L2224/10145 ,  H01L2224/0401 ,  H01L2224/81203 ,  H01L2224/16227 ,  H01L2224/14177

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate having one or more solder structures. A first set of solder structures is located in a peripheral region of the substrate and a second set of solder structures is located in a central region of the substrate. A height of individual ones of the second set of solder structures is greater than a height of individual ones of the first set of solder structures. A die having a first side and a second side includes one or more conductive die pads on the first side, where individual ones of the conductive die pads are on individual ones of the first set solder structures and on individual ones of the second set solder structures. A die backside layer is on the second side of the die.

公开(公告)号：US20230317545A1

公开(公告)日：2023-10-05

申请号：US17710507

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Pilin Liu ,  Feras Eid ,  Michael Baker ,  Wenhao Li ,  Zhaozhi Li

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/367 ,  H01L24/16 ,  H01L24/17 ,  H01L24/08 ,  H01L24/09 ,  H01L24/81 ,  H01L23/3732 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2224/81203 ,  H01L2224/10155 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16237 ,  H01L2224/16014 ,  H01L2224/16013 ,  H01L2224/16057 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17132 ,  H01L2224/17133 ,  H01L2224/0801 ,  H01L2224/0903 ,  H01L2224/09104 ,  H01L2224/08113

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

公开(公告)号：US20180254256A1

公开(公告)日：2018-09-06

申请号：US15762837

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Pilin Liu ,  Purushotham Kaushik Muthur Srinath ,  Deepak Goyal

IPC: H01L23/00 ,  B23K35/26 ,  B23K35/02 ,  H01L21/768

CPC classification number: H01L24/81 ,  B23K35/0222 ,  B23K35/0233 ,  B23K35/0238 ,  B23K35/26 ,  B23K35/264 ,  H01L21/76843 ,  H01L23/48 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/16147 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01322

Abstract: Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).

公开(公告)号：US11387175B2

公开(公告)日：2022-07-12

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sanka Ganesan ,  Pilin Liu ,  Shawna Liff ,  Sri Chaitra Chavali ,  Sandeep Gaan ,  Jimin Yao ,  Aastha Uppal

IPC: H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532 ,  H01L23/498

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US10361167B2

公开(公告)日：2019-07-23

申请号：US15762837

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Pilin Liu ,  Purushotham Kaushik Muthur Srinath ,  Deepak Goyal

IPC: H01L23/00 ,  H01L23/48 ,  B23K35/26 ,  B23K35/02 ,  H01L21/768

Abstract: Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).

公开(公告)号：US20230317676A1

公开(公告)日：2023-10-05

申请号：US17711926

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Michael Baker ,  Feras Eid ,  Wenhao Li ,  Zhaozhi Li ,  Pilin Liu

IPC: H01L23/00 ,  B23K20/02

CPC classification number: H01L24/75 ,  H01L24/81 ,  B23K20/023 ,  H01L2224/05647 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/75983 ,  H01L2224/75984 ,  H01L2224/75985 ,  H01L2224/75312 ,  H01L2224/75252 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/75253 ,  B23K2101/40

Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) assembly including a bond head with a first thermal zone separated from a second thermal zone by a thermal separator, the thermal separator extending through a thickness of the bond head. A bond head nozzle is coupled to a first side of the bond head, where the bond head nozzle includes one or more nozzle channels extending through a thickness of the bond head nozzle.

公开(公告)号：US20230317675A1

公开(公告)日：2023-10-05

申请号：US17711925

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Michael Baker ,  Zhaozhi Li ,  Feras Eid ,  Pilin Liu ,  Wenhao Li

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L2224/81203 ,  H01L2224/75983 ,  H01L2224/75252

Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) tool including a pedestal having a convex surface to receive a package substrate, a bond head to compress a die against the package substrate, and a heat source thermally coupled to at least one of the pedestal or the bond head.

公开(公告)号：US20230317630A1

公开(公告)日：2023-10-05

申请号：US17710502

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Feras Eid ,  Michael Baker ,  Pilin Liu ,  Zhaozhi Li

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/81203

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.